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datashee t product structure silicon monolithic integrated circuit this product has no designed prot ection against radioactive rays 1/376 tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 14 001 audio 1-chip soc BM94801KUT general description the BM94801KUT is a 1-chip soc for multimedia audio systems, which supports the bluetooth a2dp, usb memory, sd memory card, and cd. this ic has a built-in arm946es processor, sdram, and various peripherals. it is designed to download programs from external serial flash rom and execute system control, file system management, audio codec, and a wide range of media control. features this ic includes the following blocks: processor ? arm946es microprocessor core memory ? sdram ? initial program rom ? program sram ? data sram ? sdram controller system ? multilayer ahb ? dma bus ? interrupt controller ? dma controller serial, media i/f ? gpio ? pin controller ? usb2.0 dual role (host/device) controller ? sd i/f ? quad spi i/f ? spi i/f (master/slave) ? i2c i/f (master/slave) ? uart i/f ? i2s input i/f ? i2s output i/f ? cd servo controllers ? cd-rom decoder ? general purpose a/d converter timer ? timer ? watchdog timer ? real time clock other ? clock generator ? reset generator ? pll package application component stereo application block figure 1. tqfp128um 16.00mm ? 16.00mm ? 1.20mm 0.4 mm pitch downloaded from: http:///
2/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 arm946es microprocessor core 32 bit risc processor operating frequency: 96 mhz (118 dmips) 8 kbyte cache 4 kbyte data cache 4 kbyte instruction cache sdram 16 mbits sdram with built-in msm56v16160k from lapis semiconductor 2 bank x 524,288 word x 16 bit initial program rom itcm rom size: 2 kbyte (512 word x 32 bit) boot program no wait access remap remapping can be implemented by writing to internal registers. shadow sram ram size: 512 byte (128 word x 32 bit) no wait access program sram itcm ram size: 64 kbyte (16,384 word x 32 bit) no wait access data sram dtcm ram size: 64 kbyte (16,384 word x 32 bit) no wait access sdram controller supports sdram supports 11 bit row address, 8-bit column address, and 1-bit bank address to sdram amba multilayer ahb 32 bit data bus arbitrates arm and dma access with an arbiter allows parallel access according to different master/slave combinations interrupt controller 32 irq interrupt lines 1 fiq interrupt line allows programmable setting of interrupt priority levels allows setting of 16 vector addresses dma controller up to 2 dma channels channel fifo depth up to 16 bytes allows programmable setting of transfer data width in the range of 1 byte to 4 bytes allows programmable setting of channel priority levels maximum block length up to 4,095 words includes 12 handshake interfaces available for assignment to channels with software supports multiblock transfers connects the master board to system bus gpio gpio0 (32 pins), gpio1 (32 pins) supports a maximum of 64 i/o pins supports the interrupt function supports external level-sensitive interrupt downloaded from: http:///
3/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 pin controller controls connection settings between pins and blocks block number of gpio pins dedicated gpio pins 20 combined gpio pins 44 one line of 2-ch i2s output 5 two lines of 2-ch i2s input 6 sdio i/f 8 spi master 4 spi slave 4 quad spi i/f 6 2-ch uart 6 2-ch i2c master/slave 4 rcr 1 usb 2.0 dual role (host/device) controller usb 2.0 compatible bit rate: high speed (480 mbps) / full speed (12 mbps) configurable for up to five transmit endpoint fifos and four receive endpoint fifos (including endpoint 0) each endpoint fifo supports bulk transfer, interrupt transfer, and isochronous transfer. 2048-byte ram for endpoint fifo sd i/f supports sdxc, sdhc, and sd cards provide access to sd card in sd bus mode allows control from the amba-ahb bus includes 512 byte data transmit/receive fifos quad spi i/f supports quad serial flash rom supports serial flash rom address up to 24 bits allows the setting of control registers from the amba-ahb bus allows direct access from the memory map of the amba-ahb bus to serial flash rom includes 32 byte data transmit/receive fifos ssi master fifo depth up to 16 words and fifo data width up to 16 bits selectable data size from 4 bits to 16 bits serial protocol supports spi from motorola includes dma handshake interface ssi slave fifo depth up to 16 words and fifo data width up to 16 bits selectable data size from 4 bits to 16 bits serial protocol supports spi from motorola includes dma handshake interface i2c i/f (master/slave) 2 ch i2c serial interface supports two speed modes - standard mode (100 kb/s) - fast mode (400 kb/s) supports i2c master and slave operation allows 7 and 10 bit address generation has built-in 32 stage transmit and receive fifos includes dma handshake interface downloaded from: http:///
4/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 uart i/f is16550-based allows various baud rate settings with software (up to 6 mbps) no support for irda fifo depthup to 32 words and fifo data width up to 8 bits incorporates a function to invert output includes dma handshake interface i2s input i/f two lines of 2-ch digital audio input i2s, eiaj format 16-bit data selectable bit clock from 32 fs, 48 fs, and 64 fs selectable input sample rate from 32 khz, 44.1 khz, and 48 khz one line of internal input from the cd servo controller maximum input rate up to 4 ? supports detection of cd-da link supports detection of cd-rom sync supports cd-rom data descrambling acquires sub-q data acquires cd-text data built-in dma i2s output i/f 2.1-ch digital audio output x 1 2 channels from decoder, 1 channel from adc i2s, eiaj format selectable output sample rate from 32 khz, 44.1 khz, 48 khz, 88.2 khz, 96 khz,176.4 khz, and 192 khz selectable data width from 16, 24, and 32 bits 64 fs bit clock supports pitch control ( ? 0.5 to ? 2.0 in 25 steps) cd servo controller supports rotation speed of cd up to 4 ? built-in preservo-amplifier with power save mode, which supports playback of cd-rw allows independent offset adjustment of ac, bd, e, and f amplifiers built-in auto-tracking and focus adjustment function built in pll and clv with a wide lock range built-in asymmetry correction function cd-rom decoder supports mode1, mode2 form1, and mode2 form2 supports ecc and edc built-in dma general purpose a/d converter 10-bit sar adc, 8 ch adc maximum frequency for a/d conversion up to 736 khz (for 1 ch converter) timer supports five independent programmable timer functions each timer supports time width up to 32 bits each timer supports independent interrupt signal watchdog timer composed of a counter having a set cycle to monitor the occurrence of timeout event counter width up to 32 bits the counter counts down from the set value and sets timeout occurrence when it reaches zero real time clock 32 bit programmable timer supports interrupt signals external 32.768 khz crystal oscillator (external 32.768 khz x'tal) downloaded from: http:///
5/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 remote controller receiver (rcr) converts infrared remote control signal to code compatible with the signal format of the a ssociation for electric home appliances clock generator supplies clocks to indivi dual internal blocks allows on/off control of clocks to individual blocks generates master audio clocks supports power-down mode reset generator generates a pulse to be supplied to individual blocks pll generates 192 mhz clock used to generate system clocks generates 135.4752 mhz and 147.456 mhz cl ocks used to generate audio clocks power supply voltage i/o power supply voltage: 3.3v (3.0 to 3.5v) analog power supply voltage: 3.3v (3.0 to 3.5v) (used for sdram, cd servo, and usb) digital core power supply voltage: 1.55v (1.5 to 1.6v) (used for digital core and adc) downloaded from: http:///
6/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 pin description pin assignment _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ figure 2. pin assignment diagram downloaded from: http:///
7/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 pin description no. block pin name i/o function 1 reset resetx i h: release reset, l: reset 2 sdio sd_wp i sd card i/f wp detect 3 power dvddio - vdd (3v) 4 sdio sd_con i sd card i/f connection detect 5 sdio sd_dat1 i/o sd card i/f data i/o (1) 6 sdio sd_dat0 i/o sd card i/f data i/o (0) 7 sdio sd_clk o sd card i/f clock output 8 sdio sd_cmd o sd card i/f command output 9 sdio sd_dat3 i/o sd card i/f data i/o (3) 10 sdio sd_dat2 i/o sd card i/f data i/o (2) 11 power vddq - sdram power supply (vdd1) 12 power vssq - sdram ground 13 gpio gpio0 i/o gpio i/o (0) 14 gpio gpio1 i/o gpio i/o (1) 15 gpio gpio2 i/o gpio i/o (2) 16 power svss - sdram ground 17 power svdd - sdram power supply (vdd1) 18 power dvdd - vdd (1.5v) 19 power dvss - ground 20 power vssq - sdram ground 21 master sio mscs o sio ma ster chip select output 22 master sio msdi i sio master data input 23 master sio msclk o sio master clock output 24 master sio msdo o sio master data output 25 slave sio sscs i sio sl ave chip select input 26 slave sio ssdi i sio slave data input 27 slave sio ssclk i sio slave clock input 28 slave sio ssdo o sio slave data output 29 gpio gpio3 i/o gpio i/o (3) 30 gpio gpio4 i/o gpio i/o (4) 31 gpio gpio5 i/o gpio i/o (5) 32 gpio gpio6 i/o gpio i/o (6) 33 power vdd_adc - adc power supply (1.5v) 34 adc adin0 i adc analog input (0) 35 adc adin1 i adc analog input (1) 36 adc adin2 i adc analog input (2) 37 adc adin3 i adc analog input (3) 38 adc adin4 i adc analog input (4) 39 adc adin5 i adc analog input (5) 40 adc adin6 i adc analog input (6) 41 adc adin7 i adc analog input (7) 42 power vss_adc - adc ground 43 cddsp ana_moni0 o input & analog monitor output 44 cddsp ana_moni1 o input & analog monitor output 45 cddsp rfi i rf output capacitance coupling re-input 46 cddsp eqo o output after rf equalizer 47 cddsp ad_moni0 o input & monitor signal output 48 cddsp ad_moni1 o input & monitor signal output 49 power avdd1 - rf analog power supply 50 cddsp ac i a ? c voltage input 51 cddsp bd i b ? d voltage input 52 cddsp vbias o bias level 53 power agnd1 - rf analog ground 54 cddsp e i e voltage input 55 cddsp f i f voltage input 56 cddsp pd i apc photo detector input 57 cddsp ld o apc laser drive output 58 cddsp asy i asymmetric correction 59 cddsp pco o pll pco output 60 cddsp fco o pll fco-dac output 61 cddsp fdout o focus drive output 62 cddsp tdout o tracking drive output 63 cddsp sdout o sled drive output 64 cddsp clvout o clv drive output 65 cddsp clk88 o clock output for driver ic downloaded from: http:///
8/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 pin description - continued no block pin name i/o function 66 jtag jtag tdo o jtag tdo 67 jtag jtag tck i jtag tck 68 jtag jtag tms i jtag tms 69 jtag jtag tdi i jtag tdi 70 jtag jtag trst i jtag trst 71 power dvss - ground 72 gpio gpio7 i/o gpio i/o (7) 73 gpio gpio8 i/o gpio i/o (8) 74 gpio gpio9 i/o gpio i/o (9) 75 i2c scl0 i/o i 2 c clock i/o (0) 76 i2c sda0 i/o i 2 c data i/o (0) 77 i2s out mclko1 o digital audio master clock output (1) 78 power dvddio - vdd (3v) 79 power svdd - sdram power supply (vdd1) 80 power svss - sdram ground 81 i2s out datao1 o digital audio data output (1) 82 i2s out bcko1 o digital audio bit clock output (1) 83 i2s out lrcko1 o digital audio channel clock output (1) 84 i2s out datao2 o digital audio data output (2) 85 power dvss - ground 86 flash fl_dat2 i/o serial flash rom i/f data i/o (2) 87 flash fl_dat1 i/o serial flash rom i/f data i/o (1) 88 flash fl_cs o serial flash rom i/f command output 89 flash fl_dat3 i/o serial flash rom i/f data i/o (3) 90 flash fl_clk o serial ffash rom i/f clock output 91 flash fl_dat0 i/o serial flash rom i/f data i/o (0) 92 power dvdd - vdd (1.5v) 93 gpio gpio10 i/o gpio i/o (10) 94 gpio gpio11 i/o gpio i/o (11) 95 gpio gpio12 i/o gpio i/o (12) 96 power avddc - usb power supply (vdd1) 97 usb usb_dm1 i/o usb d- i/o 98 usb usb_dp1 i/o usb d+ i/o 99 power avssc - usb ground 100 usb rexti i pin is connected to usb reference voltage and avssc pin via a 12.3-k ? usb bias resistor. connect a resistor of 12.3-k ? 1% to gnd. only using usb full sp eed, the resistor of 12.3-k ? 5% is approvable on the usb media playability check. 101 uart uart0_rxd i uart0 receive data 102 uart uart0_txd o uart0 transmit data 103 uart uart0_rts o uart0 transfer request 104 uart uart0_cts i uart0 clear request 105 gpio gpio13 i/o gpio i/o (13) 106 gpio gpio14 i/o gpio i/o (14) 107 gpio gpio15 i/o gpio i/o (15) 108 gpio gpio16 i/o gpio i/o (16) 109 gpio gpio17 i/o gpio i/o (17) 110 i2s in lrcki1 i digital audio channel clock input (1) 111 i2s in bcki1 i digital audio bit clock input (1) 112 i2s in datai1 i digital adio data input (1) 113 i2s in lrcki2 i digital audio channel clock input (2) 114 i2s in bcki2 i digital audio bit clock input (2) 115 i2s in datai2 i digital audio data input (2) 116 gpio gpio18 i/o gpio i/o (18) 117 gpio gpio19 i/o gpio i/o (19) 118 i2c scl1 i/o i 2 c clock i/o (1) 119 i2c sda1 i/o i 2 c data i/o (1) 120 rcr rcr i remote controller signal input 121 uart uart1_rxd i uart1 receive data 122 uart uart1_txd o uart1 transmit data 123 power dvss - ground 124 clock xin_32k i x'tal (32.768 khz) connection input 125 clock xout_32k o x'tal (32.768khz) connection output 126 test tmode i test mode terminal: this pin is connected to gnd. 127 clock xin_pll i x'tal (16.9344mhz) connection input 128 clock xout_pll o x'tal (16.9344mhz) connection output downloaded from: http:///
9/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 electrical characteristics absolute maximum ratings (ta ? 25 ? c) parameter symbol rating unit remark input voltage (analog, i/o) v dd1max ? 0.3 to +4.5 v dvddio, vddq, svdd, avdd1, avddc input voltage (core) v dd2max ? 0.3 to +2.1 v dvdd, vdd_adc input voltage v in ? 0.3 to v dd1 ? 0.3 v storage temperature range tstg ? 55 to +125 ? c operating temperature range topr ? 40 to +75 ? c using usb high speed operating temperature range topr ? 40 to +85 ? c using usb full speed power dissipation (n o t e 1) pd1 1.96 w (note 1) derating is done in 19.6 mw/c for operation above ta 25 c mount on 2-layer 114.3mm x 76.2mm x 1.6mmt board (bottom side copper layer 74.2mm x 74.2mm) caution: operating the ic over the absolute maximum ratings may damage the ic. the damage can either be a short circuit between pins or an open circuit between pins and the internal circuitry. therefore, it is important to consider circuit protection measures such a s adding a fuse, in case the ic is operated over the absolute maximum ratings. recommended operating conditions (ta=25c) parameter symbol rating unit remark input voltage (analog, i/o) v dd1 3.0 to 3.5 v dvddio, vddq, svdd, avdd1, avddc input voltage (core) v dd2 1.55 to 1.65 v dvdd, vdd_adc (using usb high speed) input voltage (core) v dd2 1.5 to 1.65 v dvdd, vdd_adc (using usb full speed) electrical characteristics (unless otherwise noted, ta ? 25 ? c, v dd1 ? 3.3v, v dd2 ? 1.55v, v ssq ? sv ss ? dv ss ? v ss_adc ? agnd1 ? av ssc ? 0v, xin_pll ? 16.9344 mhz, xin_32k ? 32.768 khz, rexti pins eeternal resistance=12.3k ? 1% (note 8) ) parameter symbol rating unit conditions suitable pin min typ max operating current consumption (vdd1) i ddhs1 110 180 ma using usb high speed operating current consumption (vdd1) i ddfs1 60 130 ma using usb full speed operating current consumption (vdd2) i dd2 100 200 ma input h voltage v ih v dd1 * 0.7 v dd1 v (note 1) input l voltage v il dv ss v dd1 *0.3 v (note 1) output h voltage 1 v oh1 v dd1 - 0.4 v dd1 v i oh ? ? 1.6ma (note 2) output l voltage 1 v ol1 0 0.4 v i ol ? 1.6ma (note 2) output l voltage 2 v ol2 0 0.4 v i ol ? 3.6ma (note 3) output h voltage 3 v oh3 v dd1 - 0.4 v dd1 v i oh ? ? 0.6ma (note 4) output l voltage 3 v ol3 0 0.4 v i ol ? 0.6ma (note 4) output h voltage 4 v oh4 v dd1 - 1.0 v dd1 v i oh ? ? 0.6ma (note 5) output l voltage 4 v ol4 0 1.0 v i ol ? 0.6ma (note 5) idle pull-up resistance r pu _ id 0.9 - 1.575 k ? (n o t e 7 ) rx pull-up resistance r pu _ rx 1.425 - 3.09 k ? (n o t e 7 ) pull-down resistance r pd 14.25 - 24.8 k ? (n o t e 6) hs idle voltage v hsoi -10 5 25 mv (n o t e 6) hs high voltage v hsoh 360 - 440 mv (n o t e 6) hs low voltage v hsol -10 5 25 mv (n o t e 6) hs rx differential input sensitivity v hssq 100 - - mv (note 6) hs rx differential input range v hscm -50 - 600 mv (n o t e 6) hs disconnect judgment voltage v hsdsc 525 - 625 mv (note 6) chirp j voltage v chirpj 700 - 1100 mv measured at 45 ? output termination (note 6) chirp k voltage v chirpk -900 - -500 mv (n o t e 6) fs high output impedance z fdrh - 45 - ? (n o t e 6) fs low output impedance z fdrl - 45 - ? (n o t e 6) downloaded from: http:///
10/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 electrical characteristics C continued parameter symbol rating unit conditions suitable pin min. typ. max. fs high voltage v foh 2.8 - 3.6 v measured when pin is pulled down to av ssc using 15 k ? resistor (note 6) fs low voltage v fol 0 - 0.3 v measured when pin is pulled up to av ddc using 1.5 k ? resistor (note 6) fs rx differential input range v flcm 0.8 - 2.5 v (n o t e 6) fs rx differential input sensitivity v flsns - - 200 mv (note 6) input h voltage v husb 2 - av ddc v (n o t e 6) input l voltage v ilusb av ssc - 0.8 v (n o t e 6) a/d conversion frequency f adconv - - 736 khz f adconv ? 16.9344mhz/23 analog input voltage range v ain 0.55 0.62 0.69 v v dd _ adc ? within 1.55v ? 1% analog input voltage range v ain 0.57 0.64 0.71 v v dd _ adc ? within 1.6v ? 1% differential non-linearity dnl - - ? 5 lsb integral non-linearity inl - - ? 5 lsb (note 1) 1,2,4 to10,13 t o15,21to 32,67 to 70,72 to 77,81 to 84, 86 to 91,93 to 95,101 to122,124,127 pins (note 2) 13 to15,21 to 32,65 to 66,72 to 74,77,81 to 84,86 to 91,93 to 95,101 to 117,120 to122 pins (note 3) 75,76,118,119 pins (note 4) 4-10, pin (note 5) 125,128 pins (note 6) 97,98 pins (note 7) 98 pin (note 8) only using usb full speed, the resistor of 12.3-k ? 5% is approvable on the usb media playability check. downloaded from: http:///
11/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 electrical characteristics C continued (unless otherwise noted, ta ? 25 ? c, v dd1 ? 3.3v, v dd2 ? 1.55v, v ssq ? sv ss ? dv ss ? v ss_adc ? agnd1 ? av ssc ? 0v, xin_pll ? 16.9344 mhz, xin_32k ? 32.768 khz, r l ? 10k ? , vc ? reference) parameter symbol rating unit conditions suitable pin min typ max maximum oscillation frequency f vcoh 4.6 6.5 - mhz 1/4 of flag1 and vco output minimum oscillation frequency f vcol - 1.1 1.7 mhz 1/4 of flag1 and vco output offset voltage v fcof -50 - +50 mv fco maximum output voltage v fch 0.2 0.5 - v fco minimum output voltage v fcl - ? 0.5 ? 0.2 v fco output l voltage v pch - ? 1.0 ? 0.6 v pco output h voltage v pcl 0.6 1.0 - v pco threshold voltage v efm ? 200 - +200 mv rfi, ana_moni0, flag2 offset voltage v adof ? 140 - +140 mv ana_moni0, ana_moni1 maximum conversion voltage v adh 1.0 1.2 +1.4 v ana_moni0, ana_moni1 minimum conversion voltage v adl ? 1.4 ? 1.2 ? 1.0 v ana_moni0, ana_moni1 offset voltage v daof -80 - +80 mv fdout, tdout, sdout, clvout maximum output voltage v dah 0.8 1.2 - v fdout, tdout, sdout, clvout minimum output voltage v dal - -1.2 -0.8 v fdout, tdout, sdout, clvout maximum output current i bo - ? 1.5 - ma vbias, bias fluctuation: 200mv or less offset voltage v rfof - 0 - mv ac ,bd, eqo maximum output voltage v rfh 1.0 1.2 - v ac, bd, eqo minimum output voltage v rfl - ? 1.3 ? 1.1 v ac, bd, eqo offset voltage v feof - 0 - mv ac, bd, ana_moni0, ana_moni1 maximum output voltage v feh 1.0 1.4 - v ac, bd, ana_moni0 ,ana_moni1 minimum output voltage v fel - ? 1.4 ? 1.0 v ac, bd, ana_moni0, ana_moni1 offset voltage v teof - 70 - mv e, f, ana_moni0, ana_moni1 maximum output voltage v teh 1.0 1.4 - v e, f, ana_moni0, ana_moni1 minimum output voltage v tel - ? 1.4 ? 1.0 v e, f, ana_moni0, ana_moni1 offset voltage v asyof - 0 - mv asy ? vc, rfi, ana_moni0 (asy_test) maximum output voltage v asyh 1.1 1.4 - v asy, rfi, ana_moni0 (asy_test) minimum output voltage v asyl - ? 1.4 ? 1.1 v asy, rfi, ana_moni0 (asy_test) output voltage 1 v apc1 2.4 2.8 - v pd ? h, ld, ana_moni0 (apcref) output voltage 2 v apc2 - 0.1 0.5 v pd ? l, ld, ana_moni0 (apcref) maximum reference voltage v apch - 220 - mv pd, ld, ana_moni0 (apcref) minimum reference voltage v apcl - 145 - mv pd, ld, ana_moni0 (apcref) downloaded from: http:///
12/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 application information clock and reset clock clock name i/o function remarks xin_32k i x'tal (32.768khz) connection input terminal xout_32k o x'tal (32.768 khz) connection terminal xin_pll i x'tal (16.9344 mhz) connection input terminal xout_pll o x'tal (16.9344 mhz) connection terminal reset signal name i/o function remarks resetx i system reset input terminal release reset signal (resetx = h) 300 us after oscillati on of 32.768khz and 16.9344mhz clock inputs have become stable. (see figure 3) figure 3.reset timing item symbol rating unit remarks min typ max reset l interval t rstx 300 - - s downloaded from: http:///
13/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 1. amba 1.1. features ? consists of multilayer ahb bus matrix ? includes three ahb buses, which use arm9, dmac, and t he dmac of individual peripherals as bus masters ? includes apb-to-ahb bridge with t he bus master arbitration function ? 32-bit data bus ? arbitrates bus masters with individual peripherals ? allows parallel access according to different master/slave combinations downloaded from: http:///
14/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 1.2. description 1.2.1. block diagram the following section shows the block diagram of a system bus. figure 4. downloaded from: http:///
15/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 1.2.2. memory map the following section shows the hardware memory map. start-adr end-adr master name size (bytes) arm dmac (note) pdmac $00000000 $000007ff instruction_rom 2k $00008000 $00017fff instruction_ram 64k $10000000 $1000ffff work_ram 64k ahb $20000000 $20ffffff serial flash rom direct 16m $70000000 $700001ff shadow ram 512 $80000000 $801fffff sdram direct 2m apb $d0000000 $d00fffff wdt $d0100000 $d01fffff timer $d0200000 $d02fffff clock/power controller $d0300000 $d03fffff pin controller $d0400000 $d04fffff rtc $d0500000 $d05fffff uart0 $d0600000 $d06fffff uart1 $d0700000 $d07fffff ssi master $d0800000 $d08fffff ssi slave $d0900000 $d09fffff i2c0 $d0a00000 $d0a0ffff i2c1 $d0b00000 $d0bfffff i2s out $d0c00000 $d0cfffff cd-dsp $d0d00000 $d0dfffff adc $d0e00000 $d0efffff remap $d0f00000 $d0ffffff rcr $d1000000 $d10fffff gpio0 $d1100000 $d11fffff gpio1 $d1200000 $d12fffff resetgen $d1300000 $d13fffff i2sin/cd-rom ahb $e0000000 $e00fffff dmac $e0200000 $e02fffff (reserved) $f0000000 $f00fffff sdram controller setting $f0100000 $f01fffff quad spi controller setting $f0200000 $f02fffff sdio controller $f8000000 $f80fffff mentor usb controller $f8100000 $f81fefff usb connect detector $fff00000 $ffffffff interrupt controller (ictl) (note) dmac access size is 32 bits. 1.2.3. arm ahb arm ahb is a single-master ahb, which uses arm9 as bus master. 1.2.4. dmac ahb dmac ahb is a single-master ahb, which uses dmac as bus master. downloaded from: http:///
16/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 1.2.5. pdmac ahb pdmac ahb is a multi-master ahb, which uses pdmac and the dmac of individual peripherals as bus masters. to access individual bus masters, the arbiter selects the bus master of pdmac ahb to allow access to the sdram or arm9 dtcm space. the following table lists priority levels for the arbiter. priority level block 1 (high) i2s output 2 usb 3 sdio 4 i2s input 5 cd-rom 6 (low) (reserved) 1.2.6. apb an ahb-to-apb bridge circuit c onverts from ahb to apb format. apb allows access from arm9 and dmac to apb peripherals. mux if individual ahbs have simultaneous access to the same peripheral, mux selects a single ahb with a higher priority level and connects the ahb bus to a peripheral bus. all ahbs, except the selected ahb, enter wait state. the following table lists the levels of priority for ahb selection. priority level ahb 1 (high) pdmac ahb 2 dmac ahb 3 (low) arm9 ahb downloaded from: http:///
17/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 1.3. i/o signals pin name i/o function destination clk_i in system clock clkctr ramclk_i in ram clock clkctr nreset_i in system reset rstgen hbusreq_marm_i in ahb hbusreq master arm9 htrans_marm_i in ahb htrans master arm9 hsize_marm_i in ahb hsize master arm9 hburst_marm_i in ahb hburst master arm9 hwdata_marm_i in ahb hwrite master arm9 haddr_marm_i in ahb haddr master arm9 hwrite_marm_i in ahb hwdata master arm9 hgrant_marm_o out ahb gr ant master arm9 hready_marm_o out ahb hready master arm9 hrdata_marm_o out ahb hrdata master arm9 hresp_marm_o out ahb hrespm master arm9 hbusreq_mdmac_i in dmac ahb hbusreq master dmac htrans_mdmac_i in dmac ahb htrans master dmac hsize_mdmac_i in dmac ahb hsize master dmac hburst_mdmac_i in dmac ahb hburst master dmac hwdata_mdmac_i in dmac ahb hwrite master dmac haddr_mdmac_i in dmac ahb haddr master dmac hwrite_mdmac_i in dmac ahb hwdata master dmac hgrant_mdmac_o out dmac ah b grant master dmac hready_mdmac_o out dmac ahb hready master dmac hrdata_mdmac_o out dmac ahb hrdata master dmac hresp_mdmac_o out dmac ahb hrespm master dmac hbusreq_mx_i in peri dmac ahb hbusreq master pdmac htrans_ mx _i in peri dmac ahb htrans master pdmac hsize_ mx _i in peri dm ac ahb hsize master pdmac hburst_ mx _i in peri dmac ahb hburst master pdmac hwdata_ mx _i in peri dmac ahb hwrite master pdmac haddr_ mx _i in peri dmac ahb haddr master pdmac hwrite_ mx _i in peri dmac ahb hwdata master pdmac hgrant_ mx _o out peri dmac ahb grant master pdmac hready_ mx _o out peri dmac ahb hready master pdmac hrdata_ mx _o out peri dmac ahb hrdata master pdmac hresp_ mx _o out peri dmac ahb hrespm master pdmac hsel_marm_ setc_o out ahb hsel slave ahb htrans_setc_o out ahb htrans slave ahb hwrite_setc_o out ahb hwrite data slave ahb hsize_setc_o out ahb hsize slave ahb haddr_setc_o out ahb haddr slave ahb hwdata_setc_o out ahb hwdata slave ahb hready_marm_o out ahb hreadyi slave ahb hready_xxx_i in ahb hready out slave ahb hrdata_xxx_i in ahb hrdata slave ahb downloaded from: http:///
18/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 i/o signals C continued pin name i/o function destination hresp_xxx_i in ahb response slave ahb hsel_pdmac_dtcm_o out ahb hsel slave dtcm htrans_pdmac_o out ahb htrans slave dtcm hwrite_pdmac_o out ahb hwrite data slave dtcm hsize_pdmac_o out ahb hsize slave dtcm haddr_pdmac_o out ahb haddr slave dtcm hwdata_pdmac_o out ahb hwdata slave dtcm hburst_pdmac_o out ahb hreadyi slave dtcm hready_sdtcm_i in ahb hready out slave dtcm hrdata_sdtcm_i in ahb hrdata slave dtcm hresp_sdtcm_i in ahb responce slave dtcm psel_x out apb sel apb paddr_sapb_o out apb addr apb penable_sapb_o out apb enable apb pwrite_sapb_o out apb write enable apb pwdata_sapb_o out apb write data apb prdata_d0x_i in apb read data apb downloaded from: http:///
19/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 2. remap 2.1. features ? controls remapping (from boot memory mapping to norma l memory mapping) after completion of initialization sequence ? generates remap control signals by writing data to internal register ? connects remap control signals to ahb address decoder ? supports apb slave interface ? little-endian system 2.2. description 2.2.1. outline block diagram pclk presetn psel paddr[7:0] pwdata[31:0] pwrite penable remap remap_n prdata[31:0] figure 5. remap block 2.2.2. description for power-on reset, address 0x0000 is assigned to a program rom for initialization. this is called boot memory mapping. setting the remap control register outputs a remap signal to the ahb address recorder after completion of initialization and, subsequently, reassigns the address 0x0000 to a shadow ram. this is called normal memory mapping. 2.3. i/o signals pin name i/o function destination pclk in apb clock clock gen present in apb reset reset gen psel in apb peripheral select signal apb paddr [7:0] in apb address apb pwdata [31:0] in apb write data apb pwrite in apb write signal apb penable in apb enable signal apb prdata [31:0] out apb read data apb remap_n out remap signal ahb downloaded from: http:///
20/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 2.4. register 2.4.1. memory map 2.4.2. register detail remapmode remap setting register name address offset width reset remapmode 0x00 1 bit 0x0 bits name direction reset description 0 remapmode mode r/w 0x0 setting this register to 1 makes remapping execution possible. 0: boot memory mapping 1: normal memory mapping downloaded from: http:///
21/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 3. sdram controller 3.1. feature ? sdram is supported. ? supports 11 bit row address, 8 bit column address, and 1 bit bank address to sdram ? sdram timing is programmable. ? the sdram auto-refresh function and refresh timing can be arbitrarily set. ? supports power-down mode of sdram 3.2. description 3.2.1. fifo the memory controller has four "fifo addresses" and eight "fifo data" on the ahb interface side. ahb address for miu (memory interface unit) is stored in fifo address for decoding. data written in memory and control information generated during burst transfer are stored in fifo data. the depth of fifo is determined depending on the delay value of sdram, which contains the refresh, pre-charge, read latency and write latency etc. 3.2.2. read_pipe/write_pipe read_pipe consists of flip-flops for memory controller, which are used to safely decode read data from sdram. write_pipe uses a flip-flop to meet the setup time for writing data to sdram. ffs are inserted in all output signals to sdram. _ ___ __ _ ___ ___ hclk isdram_clk _ __ __ _ _ _ figure 6. read_p ipe/write_pipe downloaded from: http:///
22/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 3.2.3. sdram connection of sdram interface and sdram the pin characteristic in the sdram interface is shown in the table below. sdram interface pin characteristic p i n n a m e f u n c t i o n d i r e c t i o n a c t i v e s t a t e sdclk sdram clock signal o clock sdcke sdram clock enable signal o high cs3 - cs0 external ram chip select ol o w ras sdram row address enabl e ol o w cas sdram column address enable o low sdwr sdram write signal o low ba1 - ba0 sdram bank address o address m_pre_bit sdram pre-charge bit (connected to 10-bit address) o address a ddr22 - addr0 sdram addresses o address data31 - data0 sdram data bus i/o data dqm3 - dqm0 sdram data mask o high sdram controller's sdram initialization sequence because of the default memory allocation in sdram, hw does the sdram initialization sequence automatically after power-on reset. however, sdram access should be done after register sctlr[0] becomes 0. the flow of the initialization sequence is shown in the figure below. (1) after power on, sdclk is enabled and nop state is maintained during t_init. (2) pre-charging of all banks is done. (3) auto-refresh operation is done num_int_ref times. (4) afterwards, the sdram mode register is set. moreover, after the initialization sequence ends, writing 1 to register sctlr[0] can execute the initialization sequence operation again. figure 7. sdram initialization sequence downloaded from: http:///
23/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 about sdram controller's sdram mode register the mode register is updated during initialization. afterwards, mode register update is done by writing 1 to the 9-bit sdram control register. the sdram controller can change the cas latency with sdram timing register as shown in the figure below. however, it is necessary to update the mode register when the value of controllers cas latency is changed. data cannot be read correctly. only burst length of 4 and sequential burst type are supported. however, data transfer is achieved by repeat ing four bursts and burst stops. a 1 0a 9a 8a 7a 6a 5 a 4 a 3 a 2 a 1 a 0 bt 0010 a 6 a 5 a 4 000001 010 011 100 101 110 111 cas latency reserved 1 burst length reserve d 000 c a s l a t e n c y reserved reserved 23 4 reserved figure 8. definition of mode register sdram controller's sdram command the sdram commands are shown in the table below. sdram command truth table f u n c t i o n s y m b o l c k e d q m c s r a s c a s w e detect nop xxhxxx no operation nop xxlhhh read read xxlhlh write write xxlhll bank activate a ct xxllhh pre-charge pre xxllhl a uto-refresh ref xxlllh mode register set mrs xxllll self refresh entry ref lxlllh self refresh exit - hxhxxx power down entry - lxxxxx power down exit - hxhxxx data write / output enable - hlxxxx data write / output disable - hhxxxx downloaded from: http:///
24/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 read/write read and write operations are executed through this command. burst terminate inputting the burst stop command during read or write cycle ends burst read or write operation. pre-charge pre-charge state is executed until operation to a present row address is ended and operation to another row address begins. the device automatically returns to idle state when pre-charge command has finished. auto refresh auto-refresh command can only be executed when all the banks of the device are in idle state. a specific row address in all the banks is selected when auto-refresh command is inputted and refresh operation is executed. the device automatically returns to idle state when refresh operation has finished executing. mode register set the value of the mode register is updated through addr ess (a0-a10) when mode register set command is inputted. mode register set command can only be executed when all banks are in idle or suspend state. self refresh self-refresh command, like the auto-refresh command, can only be executed when all banks of the device are idle. during operation, the device refresh automatically. refresh operation need not be executed from outside. after self-refresh operation, the device automatically returns to idle state. power down mode device enters power down mode when sdcke becomes low at idle state. all inputs, except sdclk and sdcke, are turned off. during this mode, devices power consumption is decr eased. to return to previous state (idle or active state), sdcke should be made high. downloaded from: http:///
25/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 the sdram controller's read/write access data transmission to sdram is done by 4 consecutive burst operations. the read/write timing of sdram is shown in the figure below. as shown in figure 10, 4 burst operations are also needed to execute single write. in this case, dqm is set to high (4hf) to mask the data to be written. moreover, in figur e 11, for writing 8 burst data, 4 burst operations are repeated. [] figure 9. write transfer of four bursts [] figure 10. single data write transfer [] [] figure 11. data write transfer of eight bursts downloaded from: http:///
26/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 figure 12 is the case where 4 burst read op erations are performed by cas latency =2. figure 13is the case where 4 burst read o perations are performed by cas latency =3. figure 14 is the case where 8 burst read op erations are performed by cas latency =2. [] = figure 12. data read of four bursts (cas latency = 2) [] = figure 13. data read of four bursts (cas latency = 3) figure 14. data read of eight bursts (cas latency = 2) [] = downloaded from: http:///
27/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 sdram low power consumption mode the sdram controller supports power down mode, self-refresh mode, as well as low power consumption mode. by writing 1 to sdram control register sctlr[2], the device goes to power down mode. by writing 1 to sdram control register sctlr[1], the device goes to self-refresh mode. device will exit any of these modes by clearing the sdram control register (sctlr = 0). power down mode when device is in power down mode, sdram clock is disabled, which results to lower power consumption. if sdram control register sctlr[2] = 1, clock enable (cke) is set to low. at this point, power down mode will start. refer to the figure below. to return to normal operation, clear register sctlr[2], and cke is set to high. moreover, when in power down mode, during refresh cycle, power down mode is cancelled while device performs refresh operation. when refresh operation has finished executing, device returns to power down mode again. at least one sdclk cycle should be supplied to sdram before setting cke to high. ? ??? ?_? ???_ ? ?? figure 15. power down mode self-refresh mode like in power down mode, when device is in self-refresh mode, clock is disabled and power consumption becomes lower. refresh operation is automatically execut ed using the refresh counter inside sdram. this mode takes effect when sdram is not accessed for a long time. figure 16 shows the timing diagram during self-refresh mode. when sdram control register sctlr[1] is set to 1, clock enable (cke) is set to low. self-refresh command is inputted and device enters self-refresh mode, as shown in the figure. to return to normal operation, clear register sctlr[1], and cke is set to high. at least one sdclk cycle should be supplied to sdram before setting cke to high. ?? ? figure 16. self-refresh mode about the address translation the figure shows the correspondence of the ahb address and the sdram address. sdram controller's default an initial value of memory cont roller's sdram is set as follows: ? width of row address: 11 bits ? width of column address: 8 bits ? number of banks: 2 ? cas latency: 2 please refer to the configuration list for other settings. cloc k disabled. sel f -refresh mode cloc k disabled. powe r -down mode start power-down mode is cancelled to perform refresh return to power-down mode downloaded from: http:///
28/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 3.2.4. external memory interface figure 17. external memory interface downloaded from: http:///
29/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 3.3. i/o signal memctl hclk hresetn haddr hsel_mem hsel_reg hwrite htrans hsize hburst hready hwdata sm_clken sm_ready sm_data_width_set0 s_sda_in m_rd_data gpi remap power_down sm_power_down clear_sr_dp big_endian hready_resp hresp hrdata s_ras_n s_cas_n s_cke s_bank_addr s_sel_n s_dqm s_we_n s_sa s_scl s_rd_ready s_rd_start s_rd_pop s_rd_end s_rd_dqs_mask s_cas_latency s_read_pipe m_wr_data m_addr m_precharge_bit m_dout_valid sm_oe_n sm_we_n sm_bs_n sm_rp_n sm_wp_n sm_adv_n s_sda_out s_sda_oe_n gpo figure 18. memory controller downloaded from: http:///
30/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 pin name dir. description connection ahb interface hclk in ahb bus interface clock clock gen hresetn in ahb bus reset (active low) reset gen hsel_mem in ahb select signal (memory) ahb hsel_reg in ahb select signal (register) ahb hwrite in 0: read 1: write ahb htrans[1:0] in ahb bus transfer type ahb hsize[2:0] in ahb bus transfer size ahb hburst[2:0] in ahb bus burst type ahb hready_resp out ahb bus da ta ready response ahb hready in ahb bus data ready input ahb hresp[1:0] out ahb bus transfer response ahb haddr[31:0] in ahb address bus ahb hwdata[31:0] in ahb write data bus ahb hrdata[31:0] out ahb read data bus ahb miscellaneous signals big_endian in endian setting 0: little-endian 1: big-endian fixed to low remap in remap signal 0: normal mode 1: remap operation fixed to low gpo[7:0] out general purpose output open gpi[7:0] in general purpose input: it is possible to read this signal from the srefr register by connecting it to the flash status pin. fixed to low power_down in power saving signal received from the external power management module (sdram exclusive use): this signal is connected to the power down bit of sctlr register. 0 normal mode 1 power down mode fixed to low clear_sr_dp in self-refresh signal received from the external power management module (sdram exclusive use) fixed to low sm_power_down in power saving signal received from the external power management module (flash exclusive use):this signal is connected to the power down bit of smctlr register. fixed to low downloaded from: http:///
31/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 pin name dir. description connection scan_mode in scan mode: this signal is used to bypass an internally generated asynchronous reset with hresetn in scan mode. this signal ensures that all flip-flops in the component are controllable and observable during scan testing, during which, the signal must be asserted. at all other times, it must be de-asserted. dependencies: must be asserted during scan testing testdec scanmode debug_**** out for debugging open sdram serial presence detect eeprom interface signals s_scl out spd clock open s_sa[2:0] out spd address open s_sda_oe_n out spd output enable (active low) open s_sda_out out spd data output open s_sda_in in spd data input fixed to low sdram interface signals s_ras_n out row address select i/o s_cas_n out column address select i/o s_cke out clock enable i/o s_rd_data[15:0] in sdram read data from external sdram i/o s_wr_data[15:0] out sdram write data to external sdram refer to dw_memctl_miu_ddrwr.v file for more details i/o s_addr[10:0] out sdram address bus to external sdram (also see the m_precharge_bit pin details.) i/o s_bank_addr out bank address i/o s_dout_valid[1:0] out s_dout_valid[1]: sdram valid signal for write data to sdram s_dout_valid[0]: decides direction of data flow (low C input high C output) i/o s_sel_n out chip select i/o s_dqm[1:0] out write mode: input mask read mode: output enable i/o s_we_n out write enable i/o s_rd_ready in read data ready fixed to low s_rd_start out read command start signal open s_rd_pop out read data pop open s_rd_end out last burst data open s_cas_latency[2:0] out unnecessary (open) open s_rd_dqs_mask out dqs mask signal for sdram and read open s_read_pipe out unnecessary (open) open downloaded from: http:///
32/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 3.4. register 3.4.1. memory map 3.4.2. register detail sconr (sdram config register) offset: 0x00 width: 32 bits bits direction reset description 31:21 n/a 0x0 reserved 20 r/w 0x1 enable signal of data pin for i2cdata i/o direction switch for spd (not possible for use) 0: read 1: write 19 r/w 0x0 spd access bit (not possible for use) 18 r/w 0x1 spd clock (not possible for use) 17:15 r/w 0x0 spd address bits (not possible for use) 14:13 r/w 0x0 sdram data bus width setting 2b00: 16 bits 2b01: 32 bits 2b10: 64 bits (not possible for use) 2b11: 128 bits (not possible for use) please use this bit with a reset value. 12:9 r/w 0x7 sdram column address bit width setting 4hf: reserved 4he: 15 bits 4hd: 14 bits 4hc: 13 bits 4hb: 12 bits 4ha: 11 bits 4h9: 10 bits 4h8: 9 bits 4h7: 8 bits 4h6 to 4h0: reserved please use this bit with a reset value. 8:5 r/w 0xa sram row address bit width setting 4hf: 16 bits 4he: 15 bits 4hd: 14 bits 4hc: 13 bits 4hb: 12 bits 4ha: 11 bits 4h9 to 4h0: reserved please use this bit with a reset value. 4:3 r/w 0x0 sdram bank address width setting 2b11: 4 bits 2b10: 3 bits 2b01: 2 bits 2b00: 1 bit please use this bit with a reset value. 2:0 r/w 0x0 reserved name description address offset r/w width reset sconr sdram configuration register 0x000 r/w 32bits 0x00140f40 stmg0r sdram timing register 0 0x004 r/w 32bits 0x01999251 stmg1r sdram timing register 1 0x008 r/w 32bits 0x00017080 sctlr sdram control register 0x00c r/w 32bits 0x00001048 srefr sdram refresh register 0x010 r/w 32bits 0x000002ec smskr0 mask register 0 0x054 r/w 32bits 0x00000206 downloaded from: http:///
33/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 stmg0r (sdram timing register 0) offset: 0x04 width: 32 bits bits direction reset description 25:22 r/w t_rc-1 4h6 random read and write setting at t_rc cycle intervals 4hf: 16 clocks 4he: 15 clocks 4hd: 14 clocks 4hc: 13 clocks 4hb: 12 clocks 4ha: 11 clocks 4h9: 10 clocks 4h8: 9 clocks 4h7: 8 clocks 4h6: 7 clocks 4h5: 6 clocks 4h4: 5 clocks 4h3: 4 clocks 4h2: 3 clocks 4h1: 2 clocks 4h0: 1clock please use this bit with a reset value. 31:27 r/w t_xsr-1 0x6 interval setting to shift from self-refresh mode to active or self-refresh mode 0 to 511: 1 to 512 clocks please use this bit with a reset value. 21:18 17:14 r/w t_rcar-1 0x6 auto-refresh interval setting (t_rcar) 4hf: 16 clocks 4he : 15 clocks 4hd : 14 clocks 4hc: 13 clocks 4hb : 12 clocks 4ha : 11 clocks 4h9: 10 clocks 4h8 : 9 clocks 4h7 : 8 clocks 4h6: 7 clocks 4h5 : 6 clocks 4h4 : 5 clocks 4h3: 4 clocks 4h2 : 3 clocks 4h1 : 2 clocks 4h0: 1 clock please use this bit with a reset value. 13:12 r/w t_wr-1 0x1 interval setting from last data write to pre-charge mode 2h3: 4 clocks 2h2: 3 clocks 2h1: 2 clocks 2h0: 1 clock please use this bit with a reset value. 11:9 r/w t_rp-1 0x1 interval setting for pre-charge mode 3h7: 8 clocks 3h6: 7 clocks 3h5: 6 clocks 3h4: 5 clocks 3h3: 4 clocks 3h2: 3 clocks 3h1: 2 clocks 3h0: 1 clock please use this bit with a reset value. 8:6 r/w t_rcd -1 0x0 shortest value (duration) of read/write command after active is issued 3h7: 8 clocks 3h6: 7 clocks 3h5: 6 clocks 3h4: 5 clocks 3h3: 4 clocks 3h2: 3 clocks 3h1: 2 clocks 3h0: 1 clock please use this bit with a reset value. 5:2 r/w t_ras_min-1 0x4 shortest value (duration) of pre-charge command after active is issued 3h7: 8 clocks 3h6: 7 clocks 3h5: 6 clocks 3h4: 5 clocks 3h3: 4 clocks 3h2: 3 clocks 3h1: 2 clocks 3h0: 1 clock please use this bit with a reset value. 26 r/w cas_latency-1 0x1 first data interval (cas latency) 3h3: 4 clocks 3h2: 3 clocks 3h1: 2 clocks 3h0: 1 clock please use this bit with a reset value. 1:0 downloaded from: http:///
34/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 stmg1r (sdram timing register 1) offset: 0x08 width: 32 bits bits direction reset description 31:22 n/a 0x0 reserved 21:20 n/a 0x0 unnecessary 19:16 r/w num_init_ref-1 0x1 auto-refresh frequency upon initialization 4hf: 16 times 4he: 15 times 4hd: 14 times 4hc: 13 times 4hb: 12 times 4ha: 11 times 4h9: 10 times 4h8: 9 times 4h7: 8 times 4h6: 7 times 4h5: 6 times 4h4: 5 times 4h3: 4 times 4h2: 3 times 4h1: 2 times 4h0: 1 time please use this bit with a reset value. 15:0 r/w t_init 28800 interval setting of command after power supply is turned on [clock] please use this bit with a reset value. downloaded from: http:///
35/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 sctlr (sdram control register) offset: 0x0c width: 32 bits bits direction reset description 31:19 n/a 0x0 reserved 18 n/a 0x0 reserved 17 r/w 0x0 read data ready mode setting (not possible for use) 0 : not ready 1: read data ready signal s_rd_ready becomes high. sdram read data is outputted after read is done. 16:12 r/w open_banks- 1 0x1 number of active sdram banks maximum value: 15 minimum value: 0 please use this bit with a reset value. 11 r 0x0 sdram self-refresh mode 0: normal mode 1: self-refresh mode 10 r/w 0x0 reserved 9 r/w 0x0 mode register update bit this bit is automatically cleared when updating mode register. 0: normal mode 1: update mode 8:6 r read_pipe 0x1 number of read pipes during read data passing 5 r/w 0x0 number of refresh operation done by memory controller after sdram has finished executing self-refresh mode 0: only 1 row is refreshed after sdram finishes self-refresh operation. 1: all rows are refreshed after sdram finishes self-refresh operation. please use this bit with a reset value. 4 r/w 0x0 number of refresh operation done by memory controller before sdram enters self-refresh mode 0: only 1 row is refreshed before sdram enters self-refresh mode. 1: all rows are refreshed before sdram enters self-refresh mode. 3 r/w 0x1 pre-charge method setting on the specified row 0: immediate pre-charge: after the write/read operation, the selected row undergoes pre-charge operation. 1: delay pre-charge: after the write/read operation, selected row is kept open. please use this bit with a reset value. 2 r/w 0x0 sdram power down mode setting 0: normal mode 1: power down mode 1 r/w 0x0 sdram self-refresh mode setting 0: normal mode 1: self-refresh mode when self-refresh operation has finished executing, the memory controller clears this bit. 0 r/w 0x1 sdram initialization sequence setting 0: normal mode 1: initialization mode when initialization sequence has finished executing, memory controller clears this bit. downloaded from: http:///
36/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 srefr (sdram refresh interval register) offset: 0x10 width: 32 bits bits direction reset description 31:24 r/w connected directly to external gpi terminal (not possible for use) 23:16 r/w 0x0 connected directly to external gpo terminal (not possible for use) 15:0 r/w t_ref 0x2ec sdram refresh interval setting 748 clocks in case of 96mhz: 7.8us please use this bit with a reset value. scslr0_low (chip select register 0 low) offset: 0x14 width: 32 bits bits direction reset description 31:16 r/w 0x8000 base address chip select please use this bit with a reset value. 15:0 r/w 0x0 reserved *when n_cs = 1 is specified by the configuration, this register is deleted. smskr0 (address mask register 0) offset: 0x54 width: 32 bits bits direction reset description 31:11 r/w 0x0 reserved 10:8 r/w 0x0 timing parameter setting this signal becomes don 't care for sdram. 0: timing register 0 1: timing register 1 2: timing register 2 please use this bit with a reset value. 7:5 r/w 0x0 memory type select 2b00: sdram 2b01: sram 2b10: flash 2b11: rom please use this bit with a reset value. 4:0 r/w 0x6 memory size select 0: memory is not connected. 1: 64 kb 2: 128 kb 3: 256 kb 4: 512 kb 5: 1 mb 6: 2 mb 7: 4 mb 8: 8 mb 9: 16 mb 10: 32 mb 11: 64 mb 12: 128 mb 13: 256 mb 14: 512 mb 15: 1 gb 16: 2 gb 17: 4 gb please use this bit with a reset value. downloaded from: http:///
37/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 4. interrupt controller 4.1. features it functions as amba-ahb slave device. ahb bus width: 32 bits it corresponds to little-endian system. the interrupt input from each block is detected, and the interrupt output to cpu is controlled. the interrupt input and output are both active low. it corresponds to 32-input irq and one-input fiq (interrupt usually) (high-speed interrupt). 4.2. description 4.2.1. irq 16-stage priority controller the interrupt vector is programmable in each stage of priority. generation of software interrupt it is possible to individually enable control for each interrupt. the mask can individually control interrupt. various status registers are installed. 4.2.2. fiq the software interrupt can be generated. various status registers are installed. 4.2.3. irq interrupt output the irq interrupt output circuit is shown below. figure 19. irq interrupt generation circuit 4.2.4. irq interrupt polarity the irq interrupt input polarities are all active low. the irq interrupt output polarities are all active low. the polarity of the irq interrupt output is active low. each interrupt status is active high. 4.2.5. irq software interrupt interrupt can be forced generated from software. interrupt can be activated by setting l to the corresponding bit of the irq_intforce_i register. at initial state, all interrupts are at inactive state. 4.2.6. enable irq and irq mask it is possible to enable each interrupt input. the interrupt input can be enabled by setting h to the corresponding bit of the irq_inten_i register. at initial state, all interrupts are disabled. the mask can be set at each interrupt input. the mask can do the interrupt input by setting h to the corresponding bit of the irq_intmask_i register. at initial state, all masks are invalid. downloaded from: http:///
38/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 4.2.7. irq interrupt priority level interrupt input/priority correspondence of irq and priority irq number priority priority level value 0 high 15 1 14 2 13 14 1 15 to 31 low 0 the priority level value can be read. the priority level is set by the value of 0-15. priority level 15 becomes the highest priority, and the priority falls as the priority level value becomes smaller. priority level 0 becomes the lowest level of priority. system priority level value (0-15) can be set by the irq_plevel register. an interrupt with a lower priority level than system priority level is disregarded. the initial value of the sy stem priority level is 0. 4.2.8. irq interrupt status the following interrupt status can be read and are all active high. irq raw status (irq_rawstatus) can be read from irq_rawstatus register. irq status(irq_status) can be read from irq_status register. irqmask status (irq_maskstatus) can be read from irq_maskstatus register. irqfinal status (irq_finalstatus) can be read from irq_finalstatus register. please refer to the irq interrupt output generation circuit for content of various interrupt status. 4.2.9. irq interrupt vector the interrupt vector of each irq interrupt priority can be set. an initial value of each interrupt vector is "0". each interrupt vector sets the irq_vector_n (where 0 <= n <= 15) register. downloaded from: http:///
39/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 4.2.10. fiq interrupt output the generation circuit of the fiq interrupt output is shown below. figure 20. fiq interrupt generation circuit 4.2.11. fiq interrupt polarity the polarity of the fiq interrupt input is active low. the polarity of the fiq interrupt output is active low. if l is written in the fiq_inforce register, the software interrupt becomes active. each interrupt status is active high. downloaded from: http:///
40/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 4.2.12. fiq software interrupt interrupt can be forced generated from software. interrupt can be activated by setting l to the corresponding bit of the fiq_intforce register. at initial state, all software interrupts are at inactive state. 4.2.13. enable fiq and fiq mask it is possible to enable each interrupt input. the interrupt input can be enabled by setting h to the corresponding bit of the fiq_inten register. at initial state, all interrupts are disabled. the mask can be set to the interrupt input. the mask of the interrupt input can be done by setting h to the corresponding bit of the fiq_intmask register. at initial state, the mask is invalid. 4.2.14. fiq interrupt status the following interrupt status can be read and all are active high. fiq raw status (fiq_rawstatus) status can be read from fiq_rawstatus register. fiq status (fiq_status) status can be read from fiq_status register. fiq final status (irq_finalstatus) status can be read from fiq_finalstatus register. please refer to the fiq interrupt output generation circuit for content of various interrupt status. 4.3. i/o signal terminal name i/o description connection hclk in ahb bus clock clockgen hresetn in ahb bus reset (active low) reset gen hsel in ahb slave selection ahb hwrite in ahb write ahb htrans [1:0] in ahb transfer type ahb hsize [2:0] in ahb transfer size ahb hready in ahb ready signal ahb haddr [31:0] in ahb address ahb hwdata [31:0] in ahb write data ahb hresp [1:0] out ahb slave response ahb hready_resp out ahb tranfer completion ahb hrdata [31:0] out ahb read data ahb irq_intsrc [22:0] in irq interrupt source the following are detailed. fiq_intsrc in fiq interrupt source watchdog timer irq_n out irq interrupt (active low) arm fiq_n out fiq interrupt (active low) arm list of irq interrupt connection destination terminal name connection terminal name connection irq_intsrc[0] timer0 irq_intsrc[1] timer1 irq_intsrc[2] timer2 irq_intsrc[3] timer3 irq_intsrc[4] timer4 irq_intsrc[5] rtc irq_intsrc[6] uart0 irq_intsrc[7] uart1 irq_intsrc[8] ssi_m irq_intsrc[9] ssi_s irq_intsrc[10] i2c0 irq_intsrc[11] i2c1 irq_intsrc[12] gpio0 irq_intsrc[13] gpio1 irq_intsrc[14] i2sout irq_intsrc[15] rcr irq_intsrc[16] dmac irq_intsrc[17] quadspi irq_intsrc[18] i2sin/cd-rom irq_intsrc[19] sdio irq_intsrc[20] usb irq_intsrc[21] usb_dmac irq_intsrc[22] usb conn downloaded from: http:///
41/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 4.4. register map 4.4.1. memory map name offset r/w width description irq_inten_l 0x00 r/w 32 irq source enable register initial value 0x0000_0000 irq_intmask_l 0x08 r/w 32 irq source mask register initial value 0x0000_0000 irq_intforce_l 0x10 r/w 32 irq forced enable register initial value 0xffff_ffff irq_rawstatus_l 0x18 r 32 irq raw status register initial value irq_status_l 0x20 r 32 irq status register initial value irq_maskstatus_l 0x28 r 32 irq mask status register initial value 0x0000_0000 irq_finalstatus_l 0x30 r 32 irq final status register initial value 0x0000_0000 irq_vector 0x38 r 32 irq vector register initial value 0x0000_0000 irq_vector_0 0x40 r/w 32 vector register 0 of irq priority interrupt initial value 0x0000_0000 irq_vector_1 0x48 r/w 32 vector register 1 of irq priority interrupt initial value 0x0000_0000 irq_vector_2 0x50 r/w 32 vector register 2 of irq priority interrupt initial value 0x0000_0000 irq_vector_3 0x58 r/w 32 vector register 3 of irq priority interrupt initial value 0x0000_0000 irq_vector_4 0x60 r/w 32 vector register 4 of irq priority interrupt initial value 0x0000_0000 irq_vector_5 0x68 r/w 32 vector register 5 of irq priority interrupt initial value 0x0000_0000 irq_vector_6 0x70 r/w 32 vector register 6 of irq priority interrupt initial value 0x0000_0000 irq_vector_7 0x78 r/w 32 vector register 7 of irq priority interrupt initial value 0x0000_0000 downloaded from: http:///
42/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 memory map C continued name offset r/w width description irq_vector_8 0x80 r/w 32 vector register 8 of irq priority interrupt initial value 0x0000_0000 irq_vector_9 0x88 r/w 32 vector register 9 of irq priority interrupt initial value 0x0000_0000 irq_vector_10 0x90 r/w 32 vector register 10 of irq priority interrupt initial value 0x0000_0000 irq_vector_11 0x98 r/w 32 vector register 11 of irq priority interrupt initial value 0x0000_0000 irq_vector_12 0xa0 r/w 32 vector register 12 irq priority interrupt initial value 0x0000_0000 irq_vector_13 0xa8 r/w 32 vector register 13 of irq priority interrupt initial value 0x0000_0000 irq_vector_14 0xb0 r/w 32 vector register 14 of irq priority interrupt initial value 0x0000_0000 irq_vector_15 0xb8 r/w 32 vector register 15 of irq priority interrupt initial value 0x0000_0000 fiq_inten 0xc0 r/w 1 fiq source enable register initial value 0x0 fiq_intmask 0xc4 r/w 1 fiq source mask register initial value 0x0 fiq_intforce 0xc8 r/w 1 fiq compulsory enable register initial value 0x1 fiq_rawstatus 0xcc r 1 fiq raw status register initial value 0x0 fiq_status 0xd0 r 1 fiq status register initial value 0x0 fiq_finalstatus 0xd4 r 1 fiq final status register initial value 0x0 irq_plevel 0xd8 r/w 32 irq system priority level register initial value 0x0 irq_pn 0xe8+ 4*n r/w 4 irq source n priority level setting register initial value 0xf-0xn (n > 15 is "0") downloaded from: http:///
43/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 4.4.2. register detail irq_inten_i irq source enable register offset 0x00 irq_intmask_i irq source mask register offset 0x08 irq_intforce_i irq forced enable register offset 0x10 irq_rawstatus_i irq raw status register offset 0x18 irq_status_i irq status register offset 0x20 bits name r/w reset description 31:0 interrupt enable enable r/w 0x0 interrupt enable bit 0: interrupt disabled 1: interrupt enabled bits name r/w reset description 31:0 interrupt mask r/w 0x0 interrupt mask bit 0: masking is not done. 1: masking is done. bits name r/w reset description 31:0 forced interruptf r/w 0xffff _ffff forced interrupt bit each bit corresponds to each forced interrupt input. if the interrupt input is set to active high, the bit that it corresponds to in this register becomes active high. 0: active low 1: active high bits name r/w reset description 31:0 interrupt sourceint r actual interrupt source 0: no interrupt 1: there is interrupt. bits name r/w reset description 31:0 interrupt status r interrupt status forced interrupt and after enable interrupt 0: no interrupt 1: there is interrupt. downloaded from: http:///
44/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 irq_maskstatus_i irq mask status register offset 0x28 irq_finalstatus_i irq final status register offset 0x30 irq_vector irq vector register offset 0x38 irq_vector_m irq priority m interrupt vector register offset 0x40 8m(m=0 to 15) fiq_inten fiq source enable register offset 0xc0 fiq_intmask fiq source mask register offset 0xc4 bits name r/w reset description 31:0 interrupt mask status r 0x0 interrupt status after mask 0: no interrupt 1: there is interrupt. bits name r/w reset description 31:0 final forced interrupt r 0x0 interrupt status after filter of priority level if the priority interrupt is not set, this register is the same as irq_maskstatus_i. 0 : no interrupt 1: there is interrupt. bits name r/w reset description 31:0 vector locationlocation r 0x0 when interrupt happens, the vector with the highest priority is shown. bits name r/w reset description 31:0 interrupt vector_m r/w 0x0 interrupt vector of priority level m bits name r/w reset description 0 fast interrupt enabled r/w 0x0 the fiq interrupt enable 0 interrupt disabled 1 interrupt enabled bits name r/w reset description 0 fast interrupt maskfast r/w 0x0 fiq interrupt mask bit 0 masking is not done. 1 masking is done. downloaded from: http:///
45/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 fiq_intforce fiq forced enable register offset 0xc8 fiq_rawstatus fiq raw status register offset 0xcc fiq_status fiq status register offset 0xd0 fiq_finalstatus fiq final status register offset 0xd4 irq_plevel irq system priority level register offset 0xd8 irq_pn irq source n priority level setting register offset 0xe8+4*n bits name r/w reset description 0 forced fast interruptff r/w 0x1 fiq forced interrupt bit this bit corresponds to the fiq_intsrc input. if the interrupt input is set to active high, the bit that it corresponds to in this register becomes active high. 0: active low 1: active high bits name r/w reset description 0 fast interrupt raw status r 0x0 fiq interrupt raw status 0: no interrupt 1: there is interrupt bits name r/w reset description 31:0 interrupt statuss r 0x0 fiq forced interrupt status after interrupt enable 0: no interrupt 1: there is interrupt. bits name r/w reset description 31:0 final forced interruptfinal r 0x0 fiq interrupt status after mask 0: no interrupt 1: there is interrupt. bits name r/w reset description 3:0 interrupt system priority level r/w 0x0 interrupt controller system priority level to irq interrupt source irq interrupt that is lower than this system priority level is disregarded. bits name r/w reset description 3:0 interrupt source n priority level r/w 0xf-0xn (n>15 is "0") priority level value to irq iinterrupt source n priority is 15 (highest) C 0 (lowest) downloaded from: http:///
46/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 5. dmac (direct memory access controller) 5.1. feature 5.1.1. summary ? it has master/slave interface in accordance with amba 2.0. ? direct memory access controller for two channels ? the width of the ahb bus is 32 bits. ? transfer from memory to memory, memory to peripheral, and peripheral to memory and peripheral to peripherals are supported. ? it is possible to connect with the peripheral of apb through the apb bridge. ? little-endian correspondence ? the master port is connected with the system bus. 5.1.2. address generation ? the addresses of the transfer source and transfer destination are programmable. ? address increment, decrement, and a fixed transfer are supported. ? three kinds of multi block transfer types are supported. ? block chaining by linked list ? automatic reload of channel register ? continuous address transfer ? the multi block transfer type can be set independently at each transfer source and transfer destination. 5.1.3. channel buffer ring ? fifo is 16-word long. ? the depth of fifo can be changed by the register. (max fifo size) ? channel fifo is composed of d-f/f. 5.1.4. channel control ? the transfer type of each channel (memory to memory and peripheral to memory, etc.) can be set. ? each channel can be programmed to be valid/invalid. ? the addresses of transfer source and transfer destination are programmable. ? channle priority is programmable. ? the burst transaction length is programmable in each channel. ? transfer can be interrupted along the way. ? the channel can be disabled without data loss. ? the bus can lock while transfer operation is taking place. ? the channel can lock while transfer operation is taking place. ? the channel is locked at the same time while locking the bus. 5.1.5. flow control ? dmac does the flow control (beginning and end of transfer). 5.1.6. handshaking ? it has 12 handshaking interfaces. ? the burst and single transactions are supported. ? the polarity of signals can be selected. 5.1.7. interrupt ? the correspondence of the interrupt output is one is to one cpu. ? each channel interrupt can be enabled or disabled. ? the timing of interrupt generation is programmable in ea ch channel (when block transfer is completed, when dma forwarding is completed, and when error occurs). ? masking can be individually set to each interrupt. downloaded from: http:///
47/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 5.2. description 5.2.1. transfer hierarchy the hierarchy of the memory transfer is shown below. figure 21. memory dma forwarding hierarchy chart ? one dma transfer level is divided into a single, two, or more block transfers. ? one block transfer is divided into amba burst and amba single transfer level. ? the block transfer becomes a basic unit of transfer on the programming. ? the transfer method can be set at every block. ? block length is at maximum when transfering data. the hierarchy of the peripheral transfer is shown below. figure 22. peripheral dma transfer hierarchy chart ? downloaded from: http:///
48/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 ? one dma transfer level is divided into single, two, or more block transfers. ? one block transfer is divided into burst transaction and single transaction. ? one transaction is divided into amba burst and amba single transfer. ? the block transfer becomes a basic unit of transfer on the programming. ? the transfer method can be set at every block. ? block length is at maximum when transferring data. ? multi block transfer there are three methods of block transfer. method used, as well as the transfer source and destination can be freely selected. these can be selected freely at each transfer source and transfer destination. 1. block chaining by linked list the transfer method of the construction of linked list (lli) in the memory the linked list is a set of registers necessary for transf er setting. the first address of the linked list, the transfer control register, and the next block (linked list pointer) are included in the linked list at the transfer source and transfer destination. linked list enable is executed when the block transfer ends. if the linked list pointer is set to values other than "0x0" by "1", the transfer of the next block is executed. the linked list is read from the address where dmac is set to the address where linked list pointer is automatically set before the block transfer begins. when set to this mode, the address register at the transfer source register and trans fer destination, the forwarding control register, and the linked list pointer register are rewritten, and the block transfer is initiated. when the link of the final block is listed, the linked list pointer ends the dma transfer by setting linked list enable of the control register "0" again. the allocation of the address of the linked list and the image chart of the block chaining are shown in next page. software constructs the linked list only in the necessary memory space, and sets the linked list block link enable. afterwards, the head of the linked list is loaded when the channel is enabled, and the multi block transfer starts. the image chart of the linked list is shown below. figure 23. block chaining by linked list [] [] [] [] downloaded from: http:///
49/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 figure 24. linked list address allocation 2. address automatic reload when set to this mode, the address at the beginning of block transfer is automatically reloaded when block transfer ends. software clears enable signal and set the register address automatic reload before beginning to transfer the final block. afterwards, dma transfer is finished. as for this mode alone, transfer of the next block is not executed un til the block transfer ends and interrupt is cleared with software (when block transfer ends, interrupt is effective). when final block transfer end interrupt signal is set, automatic reload enable bit is cleared. 3. transfer to continuous address transfer to consecutive addresses both these modes cannot be selected in the multi block transfer at the transfer source and transfer destination. use either block chaining or automatic reload. when transfer operation is exeuted on both the transfer s ouce and transfer destination to consecutive addresses, enlarge the block length and execute a single block trans fer. when transferring to a continuous address where the maximum block length is exceeded, either set the contin uous address by block chaining or execute a single block transfer two or more times. 32bit llpx [ 31 2 ] 2 b00 } base address of lli llpx loc llpx [ 31 2 ] 2 b00 } 0x4 llpx [ 31 2 ] 2 b00 } 0x8 llpx [ 31 2 ] 2 b00 } 0xc llpx [ 31 2 ] 2 b00 } 0x10 ctlx [ 63 32 ] ctlx [ 31 0 ] llpx darx sarx downloaded from: http:///
50/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 the image chart of three kinds of multi block transfers is shown below. figure 25. for the linked list block link at the forwarding former automatic operation reload and forwarding destination downloaded from: http:///
51/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 figure 26. for a continuous address at the forwarding fo rmer automatic operation reload and forwarding destination figure 27. for a continuous address at the forwarding former linked list block link and forwarding destination downloaded from: http:///
52/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 5.2.2. handshaking interface the allocation of the handshake interface is as shown in the following table. the interface of i2c and mmc can be switched with mode_sel. handshake interface no peripheral 0 uart0 (transmission) 1 uart0 (reception) 2 uart1 (transmission) 3 uart1 (reception) 4 ssi_m (transmission) 5 ssi_m (reception) 6 ssi_s (transmission) 7 ssi_s (reception) 8 i2c0 (transmission) 9 i2c0 (reception) 10 i2c1 (transmission) 11 i2c1 (reception) 5.2.3. transfer using handshaking transfer using handshaking signal device has 12 handshaking interfaces, and tr ansfer in each channel are programmable. at this time, the channel, dma_req from the peripheral and dma_single are enabled. the device waits. the burst transaction of the length set by dma_req is forwarded, and a single transaction is forwarded by dma_single. dma_ack is returned from dmac at the end of each transfer transaction. dma_finish is returned from dmac at the end of the block transfer. dmac becomes a flow controller, and flow is controlled (beginning and end of transfer). figure 28. burst transfer transaction (when dmac is a flow controller.) figure 29. single transfer transaction (dmac is a flow controller.) downloaded from: http:///
53/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 5.3. i/o signal scan_mode dmac hclk hresetn htrans haddr[31:0] hwdata[31:0] hwrite hready hrdata[31:0] hready_resp hsel hsize hresp dma_finish[15:0] dma_req[15:0] dma_ack[15:0] dma_last[15:0] dma_single[15:0] int_combined_n hrdata1 hready1 hgrant1 haddr1 hwdata1 hwrite1 hbusreq1 hlock1 htrans1 hburst1 hsize1 hprot1 hresp1 figure 30. dmac module downloaded from: http:///
54/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 terminal list of dmac module terminal name i/o description connection hclk in ahb clock clock gen hresetn in ahb reset reset gen haddr[31:0] in ahb address ahb hwdata[31:0] in ahb write data ahb hready in ahb enable signal ahb hready_resp out ahb enable signal ahb hresp out ahb response signal ahb hrdata[31:0] out ah b read data ahb hsel in ahb peripheral selection signal ahb hwrite in ahb write signal ahb hsize in ahb transfer size ahb htrans in ahb transfer control ahb haddrn out ahb address ahb burstn out ahb burst ahb hbusreqn out ahb bus request ahb hgrantn in ahb grant ahb hlockn out ahb bus lock ahb hprotn out ahb protection mode ahb hrdatan[31:0] in ahb read data ahb hreadyn in ahb enable signal ahb hrespn in ahb response signal ahb hsizen out ahb transfer size ahb htransn out ahb transfer control ahb hwdatan[31:0] out ahb write data ahb hwriten out ahb write signal ahb int_combined_n out dmac interrupt (active low) ictl dma_ack[15:0] out dma acknowledge each block dma_req[15:0] in dma request each block dma_finish[15:0] out dma completion signal open dma_single[15:0] in dma single request each block dma_last[15:0] in dma last l fixation scan_mode in scanning mode input testdec downloaded from: http:///
55/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 5.4. register 5.4.1. memory map name description address offset width reset sar0 channel 0 source address register 0x000 64 0x0 dar0 channel 0 destination address register 0x008 64 0x0 llp0 channel 0 llp address register 0x010 64 0x0 ctl0 channel 0 control register 0x018 64 0x0000000200004824 cfg0 channel 0 configuration register 0x040 64 0x0000000400000c00 sar1 channel 1 source address register 0x58 64 0x0 dar1 channel 1 destination address register 0x60 64 0x0 llp1 channel 1 llp address register 0x68 64 0x0 ctl1 channel 1 control register 0x70 64 0x0000000200004824 cfg1 channel 1 configuration register 0x98 64 0x0000000400000c20 downloaded from: http:///
56/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 memory map C continued name description address offset width reset rawtrf raw status for inttrf interrupt 0x2c0 64 0x0 rawblock raw status for intblock interrupt 0x2c8 64 0x0 rawsrctran raw status for intsrctran interrupt 0x2d0 64 0x0 rawdsttran raw status for intdsttran interrupt 0x2d8 64 0x0 rawerr raw status for interr interrupt 0x2e0 64 0x0 statustrf status for inttrf interrupt 0x2e8 64 0x0 statusblock status for intblock interrupt 0x2f0 64 0x0 statussrctran status for intsrctran interrupt 0x2f8 64 0x0 statusdsttran status for intdsttran interrupt 0x300 64 0x0 statuserr status for interr interrupt 0x308 64 0x0 masktrf mask for inttrf interrupt 0x310 64 0x0 maskblock mask for intblock interrupt 0x318 64 0x0 masksrctran mask for intsrctran interrupt 0x320 64 0x0 maskdsttran mask for intdsttran interrupt 0x328 64 0x0 maskerr mask for interr interrupt 0x330 64 0x0 downloaded from: http:///
57/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 memory map C continued name description address offset width reset cleartrf clear status for inttrf interrupt 0x338 64 0x0 clearblock clear status for intblock interrupt 0x340 64 0x0 clearsrctran clear status for intsrctran interrupt 0x348 64 0x0 cleardsttran clear status for intdsttran interrupt 0x350 64 0x0 clearerr clear status for interr interrupt 0x358 64 0x0 statusint status for each interrupt type 0x360 64 0x0 reqsrcreg source software transaction request register 0x368 64 0x0 reqdstreg destination software transaction request register 0x370 64 0x0 sglreqsrcreg source single transaction request register 0x378 64 0x0 sglreqdstreg destination single transaction request register 0x380 64 0x0 lstsrcreg source last transaction request register 0x388 64 0x0 lstdstreg destination last transaction request register 0x390 64 0x0 dmacfgreg dma configuration register 0x398 64 0x0 chenreg dma channel enable register 0x3a0 64 0x0 dmaidreg dma id register 0x3a8 64 0x1 dmatestreg dma test register 0x3b0 64 0x0 downloaded from: http:///
58/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 5.4.2. register detail dmacfgreg dma controller valid/invalid set register offset: 0x398 width: 64 bits bits direction reset description 63:1 n/a 0x0 reserved 0 r/w 0 if "1" is written, dmac is enabled. when "0" is written when there is an effective channel, the data is not guaranteed to be transferred. chenreg channel enable register offset: 0x3a0 width: 64 bits bits direction reset description 63:10 n/a 0x0 reserved 9:8 w 0x0 ch_en_we [1:0] channel write enable bit 7:2 n/a 0x0 reserved 1:0 r/w 0x0 ch_en [1:0] channel enable bits n-bit corresponds to channel n. it is possible to write to channel n only if the same bit at ch_en_we is set to 1. when an effective channel is disabled, data transfer is not guaranteed to be successful. sarx transfer former address setting register ( x = 0 to 1 ) offset: sar0 C 0x000 sar1 C 0x058 width: 64 bits bits direction reset description 63:32 n/a 0x0 reserved 31:0 r/w 0x0 each block transfer is set. moreover, it is always updated according to the address control (incri, decri, and fixation) while transferring it. cpu cannot write on a channel when it is in use. darx transfer destination address setting register ( x = 0 to 1 ) offset: dar0 C 0x008 dar1 C 0x060 width: 64 bits bits direction reset description 63:32 n/a 0x0 reserved 31:0 r/w 0x0 each block transfer is set. moreover, it is always updated according to the address control (incri, decri, and fixation) while transferring it. cpu cannot write on a channel when it is in use. downloaded from: http:///
59/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 llpx linked list pointer setting register ( x = 0 to 1 ) offset: llp0 C 0x010 llp1 C 0x068 width: 64 bits bits direction reset description 63:32 n/a 0x0 reserved 31:2 r/w 0x0 loc the first address of the following linked list. when the multi block transfer with the linked list block is executed, dmac automatically acquires the linked list from the address that has been set before the block transfer begun. moreover, the linked list address is 32 bits in length, and storing is not done for two subordinate position bits. when linked list is used 0x0 not included when the linked list is not used 0x0 included cpu cannot write on a channel when it is in use. setting this register makes chenreg effective. when setting this register, invalidate chenreg in the selected channel. 1:0 n/a 0x0 reserved downloaded from: http:///
60/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 ctlx channel control register ( x = 0 to 1 ) offset: ctl0 C 0x018 ctl1 C 0x070 width: 64 bits bits direction reset description 63:44 n/a 0x0 reserved 43:32 r/w 0x2 block_ts block register size setting software cannot write ona channel when it is in use. the number of block data transfer is specified by src_tr_width x block_ts. 31:29 n/a 0x0 reserved 28 r/w 0x0 llp_src_en linked list pointer enable for setting transfer source if this bit is set to "1" and llpx.loc is not "0x0", the multi block transfer, which uses the linked list is executed. 27 r/w 0x0 llp_dst_en linked list enable for setting transfer destination if this bit is set to "1" and llpx.loc is not "0x0", the multi block transfer, which uses the linked list is executed. 26:23 r/w 0x0 reserved 22:20 r/w 0x0 tt_fc transfer type and flow controller's set registers tt_fc transfer type flow controller 000 memory to memory dmac 001 memory to peripheral dmac 010 peripheral to memory dmac 011 peripheral to peripheral dmac 19:17 n/a 0x0 reserved 16:14 r/w 0x1 burst transaction length of transfer source setting src_msize 13:11 r/w 0x1 burst transaction length of transfer destination setting dest_msize downloaded from: http:///
61/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 ctlx C continued bits direction reset description 10:9 r/w 0x0 sinc transfer source address control address change setting while transfer transaction 2b00 = increment 2b01 = decrement 2b1x = fixed 8:7 r/w 0x0 dinc transfer destination address control address change setting while transfer transaction 2b00 = increment 2b01 = decrement 2b1x = fixed 6:4 r 0x2 src_tr_width data width at transfer source the mapping is done by "hsize" of ahb. 3b010: 32 bits 3:1 r 0x2 dst_tr_width data width at transfer destination the mapping is done by "hsize" of ahb. 3b010: 32 bits 0 r/w 0x1 int_en interrupt enable bit if this bit is set to "1", interrupt is enabled. downloaded from: http:///
62/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 cfgx channel configuration register (x = 0 to 1) offset: cfg0 C 0x040 cfg1 C 0x098 width: 64 bits bits direction reset description 63:47 n/a 0x0 reserved 46:43 r/w 0x0 dest_per connected to handshaking interface please allocate only one transfer transaction in one handshaking interface. 42:39 r/w 0x0 src_per connected to handshaking interface please allocate only one transfer transaction in one handshaking interface. 38:37 n/a 0x0 reserved 36:34 r/w 0x1 protctl driven amba hprot signal 1b1: hprot[0] protctl[1]: hprot[1] protctl[2]: hprot[2] protctl[3]: hprot[3] 33 r/w 0x0 fifo_mode sets whether to execute transfer transaction after a certain value of data or until fifo becomes empty 0: device executes single amba transfer transaction even once. 1: device waits until half of fifo becomes empty before transferring data. setting this bit to "1" raises the bus efficiency by doing burst transfer as much as possible. 32 r/w 0x0 fcmode when the transfer destination is a flow controller, this bit dictates when to do get data from the transfer source. 0: data is previously fetched without waiting for the request at the transfer destination. 1: after the request at the transfer destination is set, data is acquired from the transfer source. because this bit is a flow controller, dmac is not related. 31 r/w 0x0 reload_dst reload enable of transfer destination address when this bit is set to 1, device automatically reloads value on address register (darx) when block transfer begins at the transfer destination. 30 r/w 0x0 reload_src reload enable of transfer source address when this bit is set to 1, device automatically reloads value on address register (sarx) when block transfer ends at the transfer source. 29:20 n/a 0x0 reserved 19 r/w 0x0 src_hs_pol polarity selection of transfer source handshaking signal 0: active high 1: active low 18 r/w 0x0 dst_hs_pol polarity selection of transfer destination handshaking signal 0: active high 1: active low 17 r/w 0x0 lock_b while signal is set to 1, hlock is asserted and the bus is locked for the period with lock_b_l. 16 r/w 0x0 lock_ch while signal is set to 1, channel arbitration in dmac master interface is disabled for the period with lock_ch_l. downloaded from: http:///
63/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 cfgx C continued bits direction reset description 15:14 r/w 0x0 period of bus lock by lock_b 00: until dma transfer completion 01: until block transfer completion 1x: until transaction completion 13:12 r/w 0x0 period of channel lock by lock_ch 00: until dma transfer completion 01: until block ttransfer completion 1x: until transaction completion 11 r/w 0x1 hs_sel_src transfer source handshaking setting 0: hardware handshaking 1: software handshaking when the transfer source is a memory, this bit is disregarded. 10 r/w 0x1 hs_sel_dst transfer destination handshaking setting 0: hardware handshaking 1: software handshaking when the transfer destination is a memory, this bit is disregarded. 9 r 0x0 fifo_empty 0: fifo is empty. 1: there is data in fifo. 8 r/w 0x0 ch_susp when this bit is 1, the data reading from the transfer source is interrupted until the bit is cleared. the data that remains in fifo is transmitted at the transfer destination. it is equivalent to fifo_empty after transfer is interrupted. disabling of the channel becomes possible by setting this bit to 0 without data loss. 7:5 r/w channel number ch_prior setting of channel used in arbitration in the master interface the value of 0-5 is set for six channels. "0" becomes the lowest priority. as the channel number rises, priority level rises. 4:0 n/a 0x0 reserved rawtrf, rawblock, rawsrctran, rawdsttran, rawerr interrupt factor status register offset: rawtrf ----- 0x2c0 rawblock --- 0x2c8 rawsrctran C 0x2d0 rawdsttran C 0x2d8 rawerr ----- 0x2e0 width: 64 bits bits direction reset description 63:2 n/a 0x0 reserved 1:0 r 0x0 if the interrupt factor is active, "1" is read from the corresponding bit. rawtrf: dma transfer end interrupt rawblock: block transfer end interrupt rawsrctran: transfer source transaction end interrupt rawdsttran: transfer destination transaction end interrupt rawerr: when error occurs downloaded from: http:///
64/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 statustrf, statusblock, statussrctran, statusdsttran, statuserr interrupt factor enable status register offset: statustrf ----- 0x2e8 statusblock --- 0x2f0 statussrctran C 0x2f8 statusdsttran C 0x300 statuserr ----- 0x308 width: 64 bits bits direction reset description 63:2 n/a 0x0 reserved 1:0 r 0x0 if the interrupt factor is active, and if the interrupt is enabled, "1" is read from the corresponding bit. statustrf: dma transfer end interrupt statusblock: block transfer end interrupt statussrctran: transfer source transaction end interrupt statusdsttran: transfer destination transaction end interrupt statuserr: when error occurs masktrf, maskblock, masksrctran, maskdsttran, maskerr interrupt mask setting register offset:masktrf ----- 0x310 maskblock --- 0x318 masksrctran C 0x320 maskdsttran C 0x328 maskerr ----- 0x330 width:64 bits bits direction reset description 63:10 n/a 0x0 reserved 9:8 w 0x0 int_mask_we int_mask write enable 7:2 n/a 0x0 reserved 1:0 r/w 0x0 int_mask interrupt mask setting bit n-bit correspondsto channel n. it is only possible to write to thes e bits if int_mask_we is 1. 0: masked 1: unmasked masktrf: dma transfer end interrupt maskblock: block transfer end interrupt masksrctran: transfer source transaction end interrupt maskdsttran: transfer destination transaction end interrupt maskerr: when error occurs cleartrf, clearblock, clearsrct ran, cleardsttran, clearerr interrupt factor clear register offset: cleartrf ----- 0x338 clearblock --- 0x340 clearsrctran C 0x348 cleardsttran C 0x350 clearerr ----- 0x358 width: 64 bits bits direction reset description 63:2 n/a 0x0 reserved 1:0 w 0x0 when corresponding bit is set to 1, corresponding interrupt factors are cleared. cleartrf: dma transfer end interrupt clearblock: block transfer end interrupt clearsrctran: transfer source transaction end interrupt cleardsttran: transfer destination transaction end interrupt clearerr: when error occurs downloaded from: http:///
65/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 statusint interrupt output register offset: 0x360 width: 64 bits bits direction reset description 63:5 n/a 0x0 reserved 4 r 0x0 ored bits of statuserr register 3 r 0x0 ored bits of statusdstttan register 2 r 0x0 ored bits of statussrcttan register 1 r 0x0 ored bits of statusblock register 0 r 0x0 ored bits of statustrf register reqsrcreg transfer source transaction request register software drives dma_req in the set handshaking interface. offset: 0x368 width: 64 bits bits direction reset description 63:10 n/a 0x0 reserved 9:8 w 0x0 src_req_we src_req write enable 7:2 n/a 0x0 reserved 1:0 r/w 0x0 src_req transfer source request bit n-bit corresponds to channel n. it is only possible to write to these bits when src_req_we is set to 1. when software handshaking of the specified channel is disabled, these bits are disregarded. bits are not writable if corresponding bits of src_req_we is 0. reqdstreg transfer destination transaction request register software drives dma_req in the set handshaking interface. offset: 0x370 width: 64 bits bits direction reset description 63:10 n/a 0x0 reserved 9:8 w 0x0 dst_req_we dst_req write enable 7:2 n/a 0x0 reserved 1:0 r/w 0x0 dst_req transfer destination request bit n-bit corresponds to channel n. it is only possible to write to these bits when dst_req_we is set to 1. when software handshaking of the specified channel is disabled, these bits are disregarded. bits are not writable if corresponding bits of dst_req_we is 0. downloaded from: http:///
66/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 sglreqsrcreg transfer source single transaction request register software drives dma_single in the set handshaking interface. offset: 0x378 width: 64 bits bits direction reset description 63:10 n/a 0x0 reserved 9:8 w 0x0 src_sglreq_we src_sglreq write enable 7:2 n/a 0x0 reserved 1:0 r/w 0x0 src_sglreq transfer source single request bit n-bit corresponds to channel n. it is only possible to write to these bits when src_sglreq_we is set to 1. when software handshaking of the specified channel is disabled, these bits are disregarded. sglreqdstreg transfer destination single transaction request register software drives dma_single in the set handshaking interface. offset: 0x380 width: 64 bits bits direction reset description 63:10 n/a 0x0 reserved 9:8 w 0x0 dst_sglreq_we dst_sglreq write enable 7:2 n/a 0x0 reserved 1:0 r/w 0x0 dst_sglreq transfer destination single request bit n-bit corresponds to channel n. it is only possible to write to these bits when dst_sglreq_we is set to 1. when software handshaking of the specified channel is disabled, these bits are disregarded.. lstsrcreg transfer source transaction request register software drives dma_last in the set handshaking interface. w hen dmac is a flow controller, this register is not used. offset: 0x388 width: 64 bits bits direction reset description 63:0 n/a 0x0 reserved lstdstreg transfer destination transaction request register software drives dma_last in the set handshaking interface. w hen dmac is a flow controller, this register is not used. offset: 0x390 width: 64 bits bits direction reset description 63:0 n/a 0x0 reserved dmatestreg dmac test mode register static test mode/normal mode switch register in the ahb slave interface. offset: 0x3b0 width: 64 bits bits direction reset description 63:1 n/a 0x0 reserved 0 r/w 0x0 test_slv_if the slave interface enters the static test mode when this bit is set to "1". the value read from the register reaches the value written without fail in the static test mode. as a result, register read/write test becomes possible. downloaded from: http:///
67/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 6. gpio0/gpio1 6.1. feature ? it functions as amba-apb slave device. ? the width of the bus of apb is 32 bits. ? it corresponds to the little-endian. ? it has the data register and the i/o polarity control register for all bits of all ports. ? it corresponds to the gpio_debounce function for interrupt. ? it corresponds to the interrupt output. ? the interrupt output is outputted by integrated signals in one bit. ? the polarity of the interrupt output is active low. ? the level type and the edge type can be selected individually for each input to the interrupt. moreover, the selection of active low and active high is also possible. the state of each port in the initial state (after it resets it) is as follows. input and software control mode downloaded from: http:///
68/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 6.2. description 6.2.1. data flow and data control block description of the part gpio is shown as follows. pclkpclk pclk gpio_swportx_ddrn gpio_swportx_drn gpio_ext_portxn dw_apb_gpio memory-mapped read back data portxn n: 31 0 n shows the number of bits. figure 31. gpio block chart the i/o polarity of external i/o pad is controlled. it is also possible to read the value of external i/o pad from the register allocated to the memory map. the i/o polarity of external i/o can be set according to the gpio_swportx_ddr register. the output data to external i/o is set according to the gpio_swportx_dr register. input data from external i/o is from gpio_ext_portx register, which is possible to read. it is possible to read from gpio_ext_portx register regardless of control mode. downloaded from: http:///
69/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 6.2.2. interrupt output device can generate the interrupt signal from an external signal. the generation circuit of the interrupt output is shown below. figure 32 the interrupt is outputted by integrated signals in one bit. the polarity of the interrupt output is active low. as for the type of the interrupt input, the selection of the level detection method or the edge detection method is possible according to the gpio_inttype_level register. moreover, the selection of active low or active high is possible according to the gpio_int_polarity register. the mask can control for the interrupt input according to the gpio_intmask register. the following interrupt status can be read. all status are active high. it is possible to read from gpio_rawintstatus register interrupt status (gpio_rawintstatus) before masking. it is possible to read from gpio_intstatus register interrupt status (gpio_intstatus) after masking. 6.2.3. debounce function a short signal (gritti) is deleted from an external input signal at one cycle of external debounce clock. the debounce circuit and the timing chart chart are shown as follows. figure 33. downloaded from: http:///
70/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 figure 34. it is necessary to keep device active by two debounce clock cycles, at minimum, to take the signal value when the interrupt input signal is molded with the debounce clock. downloaded from: http:///
71/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 6.3. i/o signal figure 35. downloaded from: http:///
72/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 terminal list of gpio block terminal name i/o description connection pclk in apb bus clock clockgen pclk_intr in interrupt detection clock clockgen present in apb bus reset (active low) resetgen penable in apb enable. ahb pwrite in apb write ahb pwdata[31:0] in apb write data ahb paddr[31:0] in apb address ahb psel in apb slave selection ahb prdata[31:0] out apb read data ahb gpio_ext_porta[31:0] in data input io_mux gpio_porta_dr[31:0] out data output io_mux gpio_porta_ddr[31:0] out data i/o control io_mux gpio_intrclk_en out enable signal of input pclk_intr when interrupt enable is asserted gpio_intr_n out interrupt signal (active low) ictl scan_mode in scan mode testdec dbclk in debounce clock clockgen dbclk_res_n in debounce reset resetgen 6.4. register 6.4.1. memory map name address offset width reset gpio_swporta_dr 0x00 32 0x0000_0000 gpio_swporta_ddr 0x04 32 0x0000_0000 gpio_inten 0x30 32 0x0000_0000 gpio_intmask 0x34 32 0x0000_0000 gpio_inttype_level 0x38 32 0x0000_0000 gpio_int_polarity 0x3c 32 0x0000_0000 gpio_intstatus 0x40 32 0x0000_0000 gpio_raw_intstatus 0x44 32 0x0000_0000 gpio_debounce 0x48 32 0x0000_0000 gpio_porta_eoi 0x4c 32 0x0000_0000 gpio_ext_porta 0x50 32 0x0000_0000 gpio_ls_sync 0x60 32 0x0000_0000 gpio_id_code 0x64 32 0x0000_0000 - reserved - 0x68 gpio_ver_id_code 0x6c 32 0x3230_392a downloaded from: http:///
73/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 6.4.2. register detail a detailed content of the register is shown below. gpio_swporta_dr output data setting offset 0x00 gpio_swporta_ddr i/o polarity offset 0x04 gpio_inten interrupt enable setting offset 0x30 gpio_intmask interrupt mask setting offset 0x34 gpio_inttype_level interrupt input type setting offset 0x38 gpio_int_polarity interrupt input polarity offset 0x3c gpio_intstatus interrupt status offset 0x40 bits name direction reset description 31:0 gpio_swp orta_dr r/w 0x0 output data when port a is in output mode, this signal is outputted. bits name direction reset description 31:0 gpio_swp orta_ddr r/w 0x0 i/o polarity setting 1: output mode 0: input mode bits name direction reset description 31:0 gpio_inte n r/w 0x0 interrupt enable 0: interrupt is disabled. 1: interrupt is enabled. bits name direction reset description 31:0 gpio_intm ask r/w 0x0 mask interrupt signal 0: masking disabled 1: masking enabled bits name direction reset description 31:0 gpio_inttype_level r/w 0x0 interrupt input type 0: level type 1: edge type bits name direction reset description 31:0 gpio_int_polarity r/w 0x0 interrupt input polarity 0: active low 1: active high bits name direction reset description 31:0 gpio_intstatus r 0x0 interrupt status (after masking) 0: no interrupt 1: there is interrupt. downloaded from: http:///
74/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 gpio_rawintstatus life interrupt status offset 0x44 gpio_debounce debounce function control offset 0x48 bits name direction reset description 31:0 debounce enable r/w 0x0 debounce function control 0: debounce function is disabled. 1: the debounce function is enabled. gpio_porta_eoi life interrupt status offset 0x4c gpio_ext_porta input data register offset 0x50 gpio_ls_sync interrupt synchronous level signal offset 0x60 gpio_id_code gpio individual code offset 0x64 gpio_ver_id_code gpio version offset 0x6c bits name direction reset description 31:0 gpio_intstatus r 0x0 interrupt status (before masking) 0: no interrupt 1: there is interrupt. bits name direction reset description 31:0 gpio_porta_eoi w 0x0 edge type interrupt clear 0: there is no operation. 1: interrupt cleared bits name direction reset description 31:0 gpio_ext_porta r 0x0 it is possible to write to this register when port is in input mode. when in output mode, value of data register of port a can be read and outputted. bits name direction reset description 0 gpio_ls_sync r/w 0x0 level type interrupt synchronous setting0 : device outputs asynchronously. 1 : device outputs synchronously with pclk. bits name direction reset description 31:0 gpio_id_code r 0x0 gpio individual code bits name direction reset description 31:0 gpio_comp_vers ion r 0x0 gpio version downloaded from: http:///
75/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 7. pin controller 7.1. features it controls registers settings, which switch individu al pin signals between gpio block and other blocks. these register settings are set through pin inputs. after resetting, the gpio block is selected. 7.2. description 7.2.1. outline circuit diagram ______ ___ ______ ___ ___ ___ _ _ figure 36 7.3. i/o signals pin name i/o function destination paddr in apb address apb pwdata in apb write data apb pwrite in apb write enable apb penable in apb w/r enable apb psel in apb slave select apb pdata out apb data out apb 7.4. register 7.4.1. memory map name addressoffset width reset ctr0_ pa_sel 0x00 32 0x0000_0000 ctr1_ pb_sel 0x04 32 0x0000_0000 ctr2_ pu 0x08 32 0xffff_ffff ctr3_ pu 0x0c 32 0xffff_ffff ctr4_i2s_thr 0x10 32 0x0000_0000 ctr5 0x14 32 0x0000_0000 ctr6 0x18 32 0x0000_0000 ctr7 0x1c 32 0x0000_0000 ctr8 0x20 32 0x0000_0000 ctr9 0x24 32 0x0000_0000 ctr10 0x28 32 0x0000_0000 ctr11 0x2c 32 0xffff_ffff downloaded from: http:///
76/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 7.4.2. register detail the following section describes details of registers. ctr0_pa_sel gpio0 setting offset: 0x00 , reset: 0x0 ctr1_pb_sel gpio1 setting offset: 0x04 , reset: 0x0 ctr0[x==1 ctr0[x==0 pin block pin name i/o gpio 2 sdio sd_wp i gpio0[0 4 sdio sd_con i gpio0[1 5 sdio sd_dat1 io gpio0[2 6 sdio sd_dat0 io gpio0[3 7 sdio sd_clk o gpio0[4 8 sdio sd_cmd o gpio0[5 9 sdio sd_dat3 io gpio0[6 10 sdio sd_dat2 io gpio0[7 13 gpio gpio0 io gpio0[8 14 gpio gpio1 io gpio0[9 15 gpio gpio2 io gpio0[10 21 master sio mscs i gpio0[11 22 master sio msdi i gpio0[12 23 master sio msclk i gpio0[13 24 master sio msdo o gpio0[14 25 slave sio sscs i gpio0[15 26 slave sio ssdi i gpio0[16 27 slave sio ssclk i gpio0[17 28 slave sio ssdo o gpio0[18 29 gpio gpio3 io gpio0[19 30 gpio gpio4 io gpio0[20 31 gpio gpio5 io gpio0[21 32 gpio gpio6 io gpio0[22 72 gpio gpio7 io gpio0[23 73 gpio gpio8 io gpio0[24 74 gpio gpio9 io gpio0[25 75 i2c scl1 o gpio0[26 76 i2c sda1 io gpio0[27 77 i2s out mclko1 o gpio0[28 81 i2s out datao1 o gpio0[29 82 i2s out bcko1 o gpio0[30 83 i2s out lrcko1 o gpio0[31 ctr1[x==1 ctr1[x==0 pin block pin name i/o gpio 84 i2s out datao2 o gpio1[0 86 flash fl_dat2 io gpio1[1 87 flash fl_dat1 io gpio1[2 88 flash fl_cs o gpio1[3 89 flash fl_dat3 io gpio1[4 90 flash fl_clk o gpio1[5 91 flash fl_dat0 io gpio1[6 93 gpio gpio10 io gpio1[7 94 gpio gpio11 io gpio1[8 95 gpio gpio12 io gpio1[9 101 uart uart1_rxd i gpio1[10 102 uart uart1_txd o gpio1[11 103 uart uart1_rts o gpio1[12 104 uart uart1_cts i gpio1[13 105 gpio gpio13 io gpio1[14 106 gpio gpio14 io gpio1[15 107 gpio gpio15 io gpio1[16 108 gpio gpio16 io gpio1[17 109 gpio gpio17 io gpio1[18 110 i2s in lrcki1 i gpio1[19 111 i2s in bcki1 i gpio1[20 112 i2s in datai1 i gpio1[21 113 i2s in lrcki2 i gpio1[22 114 i2s in bcki2 i gpio1[23 115 i2s in datai2 i gpio1[24 116 gpio gpio18 io gpio1[25 117 gpio gpio19 io gpio1[26 118 i2c scl2 i gpio1[27 119 i2c sda2 io gpio1[28 120 rcr rcr io gpio1[29 121 uart uart2_rxd io gpio1[30 122 uart uart2_txd io gpio1[31 bits name direction reset description 31:0 - r/w 0x0 0: connected to gpio0 1: connected to individual blocks for correspondence between bits and blocks, refer to the table shown below. bits name direction reset description 31:0 - r/w 0x0 0: connected to gpio1 1: connected to individual blocks for correspondence between bits and blocks, refer to the table shown below. downloaded from: http:///
77/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 ctr2_pu gpio0 pull up resistor enable offset: 0x08 , reset: 0xffff_ffff ctr3_pu gpio1 pull up resistor enable offset: 0x0c , reset: 0xffff_ffff note: i2c / flash pin has no built-in pull up resistor. ctr4_i2s_thr i2s through setting offset: 0x10 , reset: 0x0 sel sel sel figure 37. bits name direction reset description 31:0 - r/w 0xffff_ ffff 0: off 1: on bits name direction reset description 31:0 - r/w 0xffff_ ffff 0: off 1: on bits name direction reset description 31:0 - r/w 0x0 0: output from i2sout 1: output lrck, bck, and data signals from i2sin ch1 to i2sout 2: output lrck, bck, and data signals from i2sin ch2 to i2sout downloaded from: http:///
78/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 8. usb 2.0 dual role (host/device) controller it has built-in usb 2.0 high/full speed host function. it has built-in usb 2.0 high/full speed device function. it functions as amba-ahb slave. the end point is composed of 5 options as follows: end point0: 64 bytes for control tranfer end point1: 512 bytes for tx transfer / 512 bytes for rx transfer end point2: 8 bytes for tx transfer / 64 bytes for rx transfer end point3: 8 bytes for tx transfer / 512 bytes for rx transfer end point4: 8 bytes for tx transfer it has built-in utmi+level2 interface. 8.1. outline 8.1.1. block chart the figure below shows the block chart of the usb host controller block. figure 38. usb host controller block 8.1.2. utm syncronization the utm syncronization block synchronizes the 60mhz clock macro cell and the controller system clock block. 8.1.3. packet encoding/decoding the packet encoding/decoding block does the encoding of transmitted header of the data packet to be added and the decoding of the received data packet. the crc addition to the transmission packet and the crc check of the reception packet are also done in this block. 8.1.4. endpoint controllers end point 0 is for state control, while end point 1-4 is for transfer control. 8.1.5. cpu interface it accesses cpu, control register, status register, and each end poi nt fifo. moreover, this block is also responsible for the sending and receiving interrupt. 8.1.6. ram controller it controls the ram, which buffers data packets between cpu and usb. the fifo pointer is acquired from endpoint controller. it is then converted to the ram addr ess pointer, and ram access control is executed. downloaded from: http:///
79/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 8.1.7. musbhdrc configuration the device has a built-in musbhdrc controller ver.2.1 made by the usb mentor company in accordance with utmi+level2. please refer to musbhdrc product specification, programmer 's guide, and user guide for details. the table below shows the composition of the end point. endpoint description ep0 tx /rx ep1 tx /rx ep2 tx /rx ep3 tx /rx ep4 tx the following table shows the configuration setting. musbhdrc config constant description configuration c_num_ept number of tx ep (ep0 is included.) 5 c_num_err number of rx ep (ep0 is included.) 4 c_ep1_def ep1 is set. enabled c_ep1_tx_def ep1 is set to tx ep. enabled c_ep1_rx_def ep1 is set to rx ep. enabled c_ep1_tor_def ep1 is shared and tx and rx share fifo. disabled c_ep1_tar_def ep1 is shared, but neither fifo, tx nor rx is shared. enabled c_ep2_xxxx ep2 it is the same as ep1. c_ep3_xxxx ep3 it is the same as ep1. c_ep4_def ep4 is set. enabled c_ep4_tx_def ep4 is set to tx ep. enabled c_ep1t_bits number of bit of byte addresses used as txfifo of ep1 9bit c_ep1r_bits number of bit of byte addresses used as rxfifo of ep1 9bit c_ep2t_bits number of bit of byte addresses used as txfifo of ep2 3bit c_ep2r_bits number of bit of byte addresses used as rxfifo of ep2 6bit c_ep3t_bits number of bit of byte addresses used as txfifo of ep3 3bit c_ep3r_bits number of bit of byte addresses used as rxfifo of ep3 9bit c_ep4t_bits number of bit of byte addresses used as txfifo of ep4 3bit c_epxxxt_bits ep5-15 2 (unused) c_epxxxr_bits ep5-15 2 (unused) c_hb_tx wideband tx iso disabled c_hb_rx wideband rx iso enabled c_vend_reg utmi vendor control register enabled 1c_vctl_bits width of utmi of v control register 4 c_vstat_bits width of utmi of v status register 8 c_dma dma controller enabled c_dynfifo_def dynamic fifo sizing disabled c_num_eps entire number of ep (ep0 is included.) 5 c_epmax_bits number of bit of maximum byte addresses of ep fifo 8 (gui generation) c_ram_bits number of bit of word addresses of ram 9 8.1.8. usb connect detector apart from musbhdrc, a connection detection circuit is added to the device for the connection under standby operation and disconnection detection. connect detection if either conn [4] or conn [6] bit is set, connection detection is enabled. usb_dp or usb_dm is monitored, and interrupt is generated at the time of connection detection. interrupt output is ored to musbhdrc interrupt. interrupt flag, conn [0], is set to 1 during the generation of interrupt. interrupt flag is cleared by writing zero. the timing diagram during a connection detection is shown in figure 39. downloaded from: http:///
80/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 c onn[4]or[6] write auto clear int erru pt en able u sb dp or dm interrupt occur int errupt flag co nn[ 0] write write clrear 12 0ms connect figure 39. connection detection disconnect detection if either conn [5] or conn [7] bit is set, disconnection detection is enabled. usb_dp or usb_dm is monitored, and interrupt is generated at the time of disconnection detection. interrupt output is ored to musbhdrc interrupt. interrupt flag, conn [1], is set to 1during the generation of interrupt. interrupt flag is cleared by writing zero. the timing diagram during a disconnection detection is shown in figure 40. co nn[ 1]o r[ 7] write auto clear interrupt enable usb dp or dm interrupt occur int errupt flag co nn[ 1] write write clrear 61 us disconnec t figure 40. disconnection detection . linestate0_latch (dp: conn [8]) and linestate0_latch (dm: conn [9]) hold linestate0 (dp: conn [2]) and the value of linestate1 (dm:conn [3]) during the generation of interrupt. the device holds it until an interrupt occurs again. downloaded from: http:///
81/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 8.1.9. usb-reset to shift to suspend mode, control signal phy of a register from the resetgen block. figure 41. reset musbhdrc after device has returned from suspend mode. the procedures of return from suspend mode are as follows: musbhdrc generates normal disconnection interrupt. musbhdrc interrupt is disabled. connection interrupt should be generated.suspend. usb interrupt occurs. check interrupt factor. set control signal suspendm to high. reset musbhdrc. wait for 1ms or more. control phyreset. setup musbhdrc again. musbhdrc generates normal connection interrupt. 8.2. i/o signals name i/o explanation connection clk_i in system clock clkctr xclk_i in transceiver macro clock clkctr usbd_clk_i in usb connection clock (32.768 khz) clkctr usbdbus_clk_i in usb connection bus clock (96 mhz / 32.768 khz) clkctr ramclk_i in ram clock clkctr mrst_i in system reset for musbc (active low) rstgen usbd_rstn_i in system reset usbc_conn, usbc_cpuif, usbtest (active low) rstgen usbphy_rstn_i in phy input reset rstgen phyrst_o out phy output reset phy usb_suspendm_i in phy input suspend rstgen suspendm_o out phy output suspend phy linestate_i in linestate phy opmode_o out mode of operation phy rxdata_i in usb data bus input phy txdata_o out usb data bus output phy txvalid_o out transmit valid phy txvalidh_o out transmit valid high phy txready_i in transmit data ready phy rxvalid_i in receive data valid phy rxvalidh_i in receive data valid high phy rxactive_i in receive active phy rxerror_i in receive error phy xcvrsel_o out tranceiver select phy termsel_o out termination select phy drvvbus_o out vbus power enable phy chrgvbus_o out charge vbus phy dischrgvbus_o out discharge vbus phy hostdiscon_i in device disconnection detect phy 1ms or more susp en dm rese t susp end re tu rn from s uspe nd downloaded from: http:///
82/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 i/o signals C continued name i/o explanation connection dppulldown_o out pulldown resistor enable (dp) phy dmpulldowm_o out pull down resistor enable (dm) phy hostmode_i in host select phy mode_o out ehci/ohci mode switch (0: ohci 1: ehci) phy oeb_o out output enable phy speed_o out speed selection during ohci mode phy vpo_o out single ended data driver input ohci phy vmo_o out single ended data driver input ohci phy vstatus_i in phy status data phy vcontrol_o out phy control data phy vcontrollloadm_o out new control information read phy ltest_mode_i in loopback test enable testdec ltest_start_i in loopback test start testdec ltest_end_o out loopback test end testdec ltest_ok_o out loopback test result ok testdec hs_mode_i in hs-mode select testdec ltest_inc_i in test_packt data select testdec phyiddq_i in usb phy iddq idle mode testdec dcotest_i in usb dc output test mode testdec dcotxv_i in usb dc output test mode txvalid testdec dcotxd_i in usb dc output test mode txdata testdec bistdone_o out memory bist done testdec bistfail_i in memory bist fail testdec bisttest_i in memory bist test testdec bistclk_i in memory bist clock testdec bistrst_i in memory bist reset testdec scanmode_i in scan mode testdec bpctr_i in bypass controller testdec mc_nint_o out cpu interrupt ictl usb_nrst_o out usb function reset rstgen sof_pulse_o out frame sync pulse phy powerdown_o out clock stop to save power phy bistret_o out memory bist retention testdec bistres_i in memory bist resume testdec pkt_start_i in test packet start testdec dma_nint_o out dma interrupt ictl ahb_hsel in ahb hsel ahb ahb_htrans in ahb htrans ahb ahb_hwrite in ahb hwrite data ahb ahb_hsize in ahb hsize ahb ahb_haddr in ahb haddr ahb ahb_hwdata in ahb hwdata ahb ahb_hreadyi in ahb hreadyi ahb ahb_hgrant in ahb hgrant ahb ahb_hreadymi in ahb hready master ahb ahb_hrdatam in ahb hrdata master ahb ahb_hrespm in ahb hrespm master ahb ahb_hreadyo out ahb hready out ahb ahb_hrdata out ahb hrdata ahb ahb_hbusreq out ahb hbusreq ahb ahb_htransm out ahb htrans master ahb ahb_hsizem out ahb hsize master ahb ahb_hburstm out ahb hburst master ahb ahb_hwritem out ahb hwrite master ahb ahb_haddrm out ahb haddr master ahb ahb_hwdatam out ahb hwdata master ahb downloaded from: http:///
83/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 8.3. register (f8000000 mentor usb controller) 8.3.1. memory map please refer to musbhdrc product specification, programmer 's guide, and user guide for details. common usb registers name description address offset width faddr function address register 00 8 power power management register 01 8 intrtx interrupt register for endpoint 0 plus tx endpoints 1 to 15 02,03 16 intrrx interrupt register for rx endpoints 1 to 15 04,05 16 intrtxe interrupt enable register for intrtx 06,07 16 intrrxe interrupt enable register for intrrx 08,09 16 intrusb interrupt register for common usb interrupts 0a 8 intrusbe interrupt enable re gister for intrusb 0b 8 frame frame number 0c,0d 16 index index register for selecting the endpoint status and control registers 0e 8 testmode usb 2.0 test modesenable 0f 8 indexed registers C peripheral mode (control status registers for endpoint selected by the index register when devctl.d2 = 0) name description address offset width txmaxp maximum packet size for peripheral tx endpoint (index register set to select endpoints 1 C 15 only) 10,11 8 csr0 control status register for endpoint 0 (index register ret to relect endpoint 0) 12,13 16 txcsr control status register for peripheral tx endpoint (index register set to select endpoints 1 C 15) rxmaxp maximum packet size for peripheral rx endpoint (index register set to select endpoints 1 C 15 only) 14,15 16 rxcsr control status register for peripheral rx endpoint (index register set to select endpoints 1 C 15 only) 16,17 16 count0 number of received bytes in endpoint 0 fifo (index register set to select endpoint 0) 18,19 16 rxcount number of bytes in peripheral rx endpoint fifo (index register set to select endpoints 1 C 15) C reserved. 1aC1b 16 C reserved. 1cC1e 16 configdata returns details of core configuration (index register is set to endpoint 0) 1f 8 fifosize returns configured size of the selected rx fifo and tx fifos (endpoints 1 C 15 only) downloaded from: http:///
84/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 indexed registers C host mode (control status registers for endpoint selected by the index register when devctl.d2 = 1) name description address offset width txmaxp maximum packet size for host tx endpoint (index register set to select endpoints 1 C 15 only) 10,11 8 csr0 control status register for endpoint 0 (index register set to select endpoint 0) 12,13 16 txcsr control status register for host tx endpoint (index register set to select endpoints 1 C 15) rxmaxp maximum packet size for host rx endpoint (index register set to select endpoints 1 C 15 only) 14,15 16 rxcsr control status register for host rx endpoint (index register set to select endpoints 1 C 15 only) 16,17 16 count0 number of received bytes in endpoint 0 fifo (index register set to select endpoint 0) 18,19 16 rxcount number of bytes in host rx endpoint fifo (index register set to select endpoints 1 C 15) txtype sets the transaction protocol and peripheral endpoint number for the host tx endpoint (index register set to select endpoints 1 C 15 only) 1a 8 naklimit0 sets the nak response timeout on endpoint 0 (index register set to select endpoint 0) 1b 8 txinterval sets the polling interval for interrupt/isoc transactions or the nak response timeout on bulk transactions for host tx endpoint (index register set to select endpoints 1 C 15 only) rxtype sets the transaction protocol and peripheral endpoint number for the host rx endpoint (index register set to select endpoints 1 C 15 only) 1c 8 rxinterval sets the polling interval for interrupt/isoc transactions or the nak response timeout on bulk transactions for host rx endpoint (index register set to select endpoints 1 C 15 only) 1d 8 C reserved. 1e 8 configdata returns details of core configuration (index register set to select endpoint 0.) 1f 8 fifosize returns the configured size of the selected rx fifo and tx fifos (endpoints 0 C 15 only) downloaded from: http:///
85/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 fifos name description address offset width ep0 fifo fifos for endpoints 0 0x20-23 32 ep1 fifo fifos for endpoints 1 0x24-27 32 ep2 fifo fifos for endpoints 2 0x28-2b 32 ep3 fifo fifos for endpoints 3 0x2c-30 32 ep4 fifo fifos for endpoints 4 0x30-33 32 additional control & configuration registers (60h C 7fh) name description address offset width devctl device control register 0x60 8 - reserved 0x61 8 vcontrol/ vstatus utmi+phy vendor register 0x6a 16 dma registers name description address offset width intr indicates pending dma interrupts 0x200 1 cntl(1) dma channel 1 control: d0: dma enable d1: direction: 0 = dma write (rx endpoint), 1 = dma read (tx endpoint) d2: dma mode d3: interrupt enable d7C4: endpoint number d8: bus error d10C9: burst mode 00 = burst mode 0 : bursts of unspecified length 01 = burst mode 1 : incr4 or unspecified length 10 = burst mode 2 : incr8, incr4 or unspecified length 11 = burst mode 3 : incr16, incr8, incr4 or unspecified length 0x204 16 addr(1) dma channel 1 ahb memory address (32 bits) 0x208 32 count(1) dma channel 1 byte count (32 bits) 0x20c 32 downloaded from: http:///
86/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 8.3.2. resister detail common usb registers faddr faddr is an 8-bit register, where the 7-bit address of peripheral transaction is written. in host mode (devctl.d2=1), this register stores the value of the peripheral device address sent through set_address command. in peripheral mode (devctl.d2=0), this register stores the address received through set_address command, which will then be used for decoding the function address in the subsequent token packets. offset: 0x00 width: 8 bits bits name direction reset description 7 unused r 0x0 unused, always returns 0 6:0 func addr r/w 0x0 function address power power is an 8-bit register, which is used to control suspend and resume signals. offset: 0x01 width: 8 bits bits name direction reset description 7 iso update r/w 0x0 when cpu set this bit to 1, the musbhdrc will wait for an sof token from the time txpktrdy is set before sending the packet. if an in token is received before an sof token, then a zero length data packet will be sent. note: this is only valid in peripheral mode. also, this bit only affects endpoints performing isochronous transfers. 6 - n/a 0x0 unused, always returns 0 5 hs enab r/w 0x1 when cpu set this bit to 1, the musbhdrc will make device operate in high-speed mode when reset. otherwise, the device will only operate in full-speed mode. 4 hs mode r 0x0 when set to 1, this read-only bit indicates that device operates in high-speed mode successfully during usb reset. 3 reset r 0x0 this bit is set when reset signaling is present on the bus. note: this bit is read/write from the cpu in host mode but read-only in peripheral mode. 2 - r/w 0x0 reserved 1 suspend mode r 0x0 in host mode, cpu sets this bit to 1 to enter suspend mode. in peripheral mode, this bit is set to 1 upon entry to suspend mode. it is cleared when the cpu reads the interrupt register. 0 - r/w 0x0 reserved downloaded from: http:///
87/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 intrtx intrtx is a 16-bit register that shows which interrupt of tx endpoints 1-15 is currently active. moreover, it shows whether the interrupt of endpoint 0 is currently active. when th is register is read, all active interrupts are cleared. offset: 0x02 width: 16 bits bits name direction reset description 15:5 - n/a 0x0 unused, always returns 0 4 ep4 tx r 0x0 tx endpoint 4 interrupt 3 ep3 tx r 0x0 tx endpoint 3 interrupt 2 ep2 tx r 0x0 tx endpoint 2 interrupt 1 ep1 tx r 0x0 tx endpoint 1 interrupt 0 ep0 tx r 0x0 endpoint 0 interrupt intrrx intrrx is a 16-bit read-only register, which shows currently ac tive interrupts of rxendpoints 1-15. when this register is read, all active interrupts are cleared. offset: 0x04 width: 16 bits bits name direction reset description 15:5 - n/a 0x0 unused, always returns 0 4 ep4 rx r 0x0 rx endpoint 4 interrupt 3 ep3 rx r 0x0 rx endpoint 3 interrupt 2 ep2 rx r 0x0 rx endpoint 2 interrupt 1 ep1 rx r 0x0 rx endpoint 1 interrupt 0 - n/a 0x0 unused, always returns 0 intrtxe intrtxe is a 16-bit interrupt enable register for endpoint 0 and txendpoints 1-4. offset: 0x06 width: 16 bits bits name direction reset description 15:5 - n/a 0x7ff unused, always returns 1 4 ep4 txe r/w 0x1 tx endpoint 4 interrupt enable 3 ep3 txe r/w 0x1 tx endpoint 3 interrupt enable 2 ep2 txe r/w 0x1 tx endpoint 2 interrupt enable 1 ep1 txe r/w 0x1 tx endpoint 1 interrupt enable 0 ep0 r/w 0x1 endpoint 0 interrupt enable intrrxe intrrxe is a 16-bit interrupt enable register for rxendpoints1-4. offset: 0x08 width: 16 bits bits name direction reset description 15:3 - n/a 0x7ff unused, always returns 1 4 ep4 rxe r/w 0x1 rx endpoint 4 interrupt enable 3 ep3 rxe r/w 0x1 rx endpoint 3 interrupt enable 2 ep2 rxe r/w 0x1 rx endpoint 2 interrupt enable 1 ep1 rxe r/w 0x1 rx endpoint 1 interrupt enable 0 - n/a 0x0 unused, always returns 0 downloaded from: http:///
88/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 intrusb intrusb is an 8-bit read-only register, which shows currently acti ve usb interrupts. when this register is read, all active interrupts are cleared. offset: 0x0a width: 8 bits bits name direction reset description 7:6 - n/a 0x0 unused, always returns 0 5 discon r 0x0 in host mode, bit is set to 1 when a device disconnection is detected. in peripheral mode, bit is set to 1 when a session ends. 4 conn r 0x0 this bit is only valid in host mode. it is set to 1 when a device connection is detected. 3 sof r 0x0 this bit is set to 1 at the beginning of each frame. 2 babble/reset r 0x0 in host mode, bit is set to 1 when babble is detected. note: only active after first sof has been sent. in peripheral mode, bit is set to 1 when reset signal is detected on the bus. 1 - r 0x0 reserved 0 suspend r 0x0 this bit is only valid in peripheral mode. it is set to 1 when suspend signal is detected on the bus. intrusbe intrusbe is an 8-bit interrupt enable register for intrusb. offset: 0x0b width: 8 bits bits name direction reset description 7:6 - n/a 0x0 unused, always returns 0 5 discon r/w 0x0 1b0: disable discon interrupt 1b1: enable discon interrupt 4 conn r/w 0x0 1b0: disable conn interrupt 1b1: enable conn interrupt 3 sof r/w 0x0 1b1: enable sof interrupt 1b0 : disable sof interrupt 2 reset r/w 0x1 1b1: enable reset interrupt 1b0 : disable reset interrupt 1 resume r/w 0x1 1b1: enable resume interrupt 1b0 : disable resume interrupt 0 suspend r/w 0x0 1b1: enable suspend interrupt 1b0 : disable suspend interrupt frame frame is a 16-bit read-only register, which holds the last received frame number. offset: 0x0c width: 16 bits bits name direction reset description 15:11 - n/a 0x0 - 10:0 frame number r 0x0 frame number index index is an 8-bit register, which determines the endpoint that can be accsessed by address 0x10-0x1f registers. offset: 0x0c width: 8 bits bits name direction reset description 7:4 - n/a 0x0 - 3:0 selected endpoint r 0x0 selected endpoint downloaded from: http:///
89/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 testmode testmode is an 8-bit register, which sets the musb hdrc test modes in high-speed operation. offset: 0x0f width: 8 bits bits name direction reset description 7 force_host r/w 0x0 the cpu sets this bit to instruct the core to enter host mode when the session bit is set. the operating speed is determined by the force_hs and force_fs bits as follows: force_hs force_fs operating speed 0 0 low speed 0 1 full speed 1 0 high speed 6 fifo_access r/w 0x0 the cpu sets this bit to transfer the packet in the endpoint 0 tx fifo to the endpoint 0 rx fifo. it is cleared automatically. 5 force_fs r/w 0x0 the cpu sets this bit either in conjunction with bit 7 above or to force the musbhdrc into full-speed mode when it receives a usb reset. 4 force_hs r/w 0x0 the cpu sets this bit either in conjunction with bit 7 above or to force the musbhdrc into high-speed mode when it receives a usb reset. 3 test_packet r/w 0x0 (high-speed mode) the cpu sets this bit to enter the test_packet test mode. in this mode, the musbhdrc repetitively transmits on the bus a 53-byte test packet. the test packet has a fixed format and must be loaded into the endpoint 0 fifo before the test mode is entered. 2 test_k r/w 0x0 (high-speed mode) the cpu sets this bit to enter the test_k test mode. in this mode, the musbhdrc transmits a continuous k on the bus. 1 test_j r/w 0x0 (high-speed mode) the cpu sets this bit to enter the test_j test mode. in this mode, the musbhdrc transmits a continuous j on the bus. 0 test_se0_nak r/w 0x0 (high-speed mode) the cpu sets this bit to enter the test_se0_nak test mode. in this mode, the musbhdrc remains in high-speed mode but responds to any valid in token with a nak. downloaded from: http:///
90/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 devctl offset: 0x60 width: 8 bits bits name direction reset description 7 b-device r this read-only bit indicates whether the musbhdrc is operating as the a device or the b device. 0:a device 1:b device this bit is only valid while a session is in progress. note: if the core is in force_host mode (i.e. a session has been started with testmode.d7 = 1), this bit will indicate the state of the hostdiscon input signal from the phy. 6 fsdev r this read-only bit is set when a connection of a full-speed or high-speed device to the port has been detected. (high-speed devices are distinguished from full-speed by checking for high-speed chirps when the device is reset.) only valid in host mode . 5 lsdev r this read-only bit is set when a connection of low-speed device to the port has been detected. only valid in host mode . 4:3 vbus[1:0] r the read-only bit encodes the following vbus level: value 0x11 is read. d4 d3 meaning 0 below session end 0 1 above session end, below avalid 1 0 above avalid, below vbusvalid 1 1 above vbusvalid 2 host mode r this read-only bit is set when the musbhdrc is acting as a host. 1 - r/w 0x0 reserved 0 session r/w when operating as an a device, this bit is set or cleared by the cpu to start or end a session. when operating as a b device, this bit is set/cleared by the musbhdrc when a session starts/ends. note: clearing this bit is forbidden when the core is not suspended. downloaded from: http:///
91/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 indexed registers csr0 in peripheral mode offset: 0x12 (with the index register set to 0) width: 16 bits bits name direction reset description 15:9 - r 0x0 unused, returns 0 when read. 8 flushfifo r/w 0x0 the cpu sets this bit to 1 to flush the next packet to be transmitted/read from the endpoint 0 fifo. the fifo pointer is reset and the txpktrdy/rxpktrdy bit (below) is cleared. note: flushfifo should only be used when txpktrdy/rxpktrdy is set. at other times, it may cause data to be corrupted. 7 servicedsetup end r/w 0x0 the cpu sets this bit to 1 to clear the setupend bit. it is cleared automatically. 6 servicedrxpkt rdy r/w 0x0 the cpu sets this bit to 1 to clear the rxpktrdy bit. it is cleared automatically. 5 sendstall r/w 0x0 the cpu sets this bit to 1 to terminate the current transaction. the stall handshake will be transmitted and then this bit will be cleared automatically. note: the fifo should be flushed before sendstall is set. 4 setupend r 0x0 this bit is set to 1 when a control transaction ends before the dataend bit has been set. an interrupt will be generated and the fifo flushed at this time. the bit is cleared when cpu sets servicedsetupend bit to 1.. 3 dataend r/w 0x0 the cpu sets this bit: 1. when setting txpktrdy for the last data packet 2. when clearing rxpktrdy after unloading the last data packet 3. when setting txpktrdy for a zero length data packet it is cleared automatically. 2 sentstall r/w 0x0 this bit is set when a stall handshake is transmitted. the cpu should clear this bit. 1 txpktrdy r/w 0x0 the cpu sets this bit after loading a data packet into the fifo. it is cleared automatically when the data packet has been transmitted. an interrupt is generated (if enabled) when the bit is cleared. 0 rxpktrdy r 0x0 this bit is set when a data packet has been received. an interrupt is generated when this bit is set. the cpu clears this bit by setting the servicedrxpktrdy bit. downloaded from: http:///
92/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 csr0 in host mode offset: 0x12 (with the index register set to 0) width: 16 bits bits name direction reset description 15:12 - r 0x0 unused. return 0 when read. 11 dis ping the cpu sets this bit to 1 to instruct the core not to issue ping tokens in data and status phases of a high-speed control transfer (for devices that do not respond to ping). 10:9 - r 0x0 unused, returns 0 when read. 8 flushfifo r/w 0x0 the cpu sets this bit to 1 to flush the next packet to be transmitted/read from the endpoint 0 fifo. the fifo pointer is reset and the txpktrdy/rxpktrdy bit (below) is cleared. note: flushfifo should only be used when txpktrdy/rxpktrdy is set. at other times, it may cause data to be corrupted. 7 nak timeout r/w 0x0 this bit is set to 1 when endpoint 0 is halted following the receipt of nak responses for longer than the time set by the naklimit0 register. the cpu should clear this bit to allow the endpoint to continue. 6 statuspkt r/w 0x0 the cpu sets this bit to 1 at the same time as the txpktrdy or reqpkt bit is set, to perform a status stage transaction. 5 reqpkt r/w 0x0 the cpu sets this bit to 1 to request an in transaction. it is cleared when rxpktrdy is set. 4 error r 0x0 this bit will be set to 1 when three attempts have been made to perform a transaction with no response from the peripheral. the cpu should clear this bit. an interrupt is generated when this bit is set. 3 setuppkt r/w 0x0 the cpu sets this bit to 1, at the same time as the txpktrdy bit is set, to send a setup token instead of an out token for the transaction. 2 rxstall r/w 0x0 this bit is set to 1 when a stall handshake is received. the cpu should clear this bit. 1 txpktrdy r/w 0x0 the cpu sets this bit to 1 after loading a data packet into the fifo. it is cleared automatically when the data packet has been transmitted. an interrupt is generated (if enabled) when the bit is cleared. 0 rxpktrdy r 0x0 this bit is set to 1 when a data packet has been received. an interrupt is generated (if enabled) when this bit is set. the cpu should clear this bit when the packet has been read from the fifo. downloaded from: http:///
93/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 count0 count0 is a 7-bit read-only register, which indicates the number of received data bytes in the endpoint 0 fifo. the value returned changes as the contents of the fifo change and is only valid while rxpktrdy (csr0.d0) is set. offset: 0x18 (with the index register set to 0) width: 8 bits bits name direction reset description 8 - n/a 0x0 - 7:0 endpoint 0 rx count r 0x0 endpoint 0 rx count configdata configdata is an 8-bit read-only register that returns information about the selected core configuration. reset value is configuration dependent. offset: 0x18 (with the index register set to 0) width: 8 bits bits name direction reset description 7 mprxe r - when set to 1, automatic concatenation of bulk packets is selected (see section 9) 6 mptxe r - when set to 1, automatic splitting of bulk packets is selected (see section 9) 5 bigendian r - when set to 1 indicates big endian ordering is selected. 4 hbrxe r - when set to 1 indicates high-bandwidth rx iso endpoint support selected. 3 hbtxe r - when set to 1 indicates high-bandwidth tx iso endpoint support selected. 2 dynfifo sizing r - when set to 1 indicates dynamic fifo sizing option selected. 1 softcone r - when set to 1 indicates soft connect/disconnect option selected. 0 utmi datawidth r - indicates selected utmi+ data width: 0: 8 bits 1: 16 bits naklimit0 (host mode only) naklimit0 is a 5-bit register that sets the number of fram es/microframes (high-speed transfers) after which endpoint 0 should timeout on receiving a stream of nak responses. (equivalent settings for other endpoints can be made through their txinterval and rxinterval registers) the number of frames/microframes selected is 2 (m-1) (where m is the value set in the register, valid values 2 C 16). if the host receives nak responses from the target for more frames than the number represented by the limit set in this register, the endpoint will be halted. note: a value of 0 or 1 disables the nak timeout function. offset: 0x1b (with the index register set to 0) width: 8 bits bits name direction reset description 7:5 - n/a 0x0 - 4:0 endpoint 0 nak limit (m) r 0x0 endpoint 0 nak limit (m) txmaxp the txmaxp register defines the maximum amount of data that can be transferred through the selected tx endpoint in a single operation. there is a txmaxp register for each tx endpoint (except endpoint 0). offset: 0x10 width: 16 bits bits name direction reset description 15:11 - n/a 0x0 - 10:0 maximum payload/transaction r/w 0x0 maximum payload/transaction downloaded from: http:///
94/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 txcsr in peripheral mode offset: 0x12 width: 16 bits bits name direction reset description 15 autoset r/w 0x0 if the cpu sets this bit, txpktrdy will be automatically set when data of the maximum packet size (value in txmaxp) is loaded into the tx fifo. if a packet of less than the maximum packet size is loaded, then txpktrdy will have to be set manually. note: this bit should not be set for either high-bandwidth isochronous endpoints or high-bandwidth interrupt endpoints. 14 iso r/w 0x0 the cpu sets this bit to enable the tx endpoint for isochronous transfers, and clears it to enable the tx endpoint for bulk or interrupt transfers. note: this bit is only valid in peripheral mode. in host mode, it always returns zero. 13 mode r/w 0x0 the cpu sets this bit to enable the endpoint direction as tx, and clears it to enable the endpoint direction as rx. note: this bit is only valid when the same endpoint fifo is used for both tx and rx transactions. 12 dmareqenab r/w 0x0 the cpu sets this bit to enable the dma request for the tx endpoint. 11 frcdatatog r/w 0x0 the cpu sets this bit to force the endpoint data toggle to switch and the data packet to be cleared from the fifo, regardless of whether an ack was received. this can be used by interrupt tx endpoints that are used to communicate rate feedback for isochronous endpoints. 10 dmareqmode r/w 0x0 the cpu sets this bit to select dma mode 1 and clears this bit to select dma mode 0. note: this bit must not be cleared either before or in the same cycle as the above dmareqenab bit is clear 9:8 C r 0x0 unused, always return 0 7 incomptx r/w 0x0 when the endpoint is being used for high-bandwidth isochronous / interrupt transfers, this bit is set to indicate where a large packet has been split into 2 or 3 packets for transmission but insufficient in tokens have been received to send all the parts. note: in anything other than a high-bandwidth transfer, this bit will always return 0. 6 clrdatatog r/w 0x0 the cpu sets this bit to 1 reset the endpoint data toggle to 0. 5 sentstall r/w 0x0 this bit is set when a stall handshake is transmitted. the fifo is flushed and the txpktrdy bit is cleared (see below). the cpu should clear this bit. 4 sendstall r/w 0x0 the cpu sets this bit to 1 to issue a stall handshake to an in token. the cpu clears this bit to terminate the stall condition. note (i) the fifo should be flushed before sendstall is set. (ii) this bit is invalid when the endpoint is being used for isochronous transfers. 3 flushfifo r/w 0x0 the cpu sets this bit to 1 to flush the latest packet from the endpoint tx fifo. the fifo pointer is reset, the txpktrdy bit (below) is cleared and an interrupt is generated. this may be set simultaneously with txpktrdy to abort the packet that is currently being loaded into the fifo. note: flushfifo should only be used when txpktrdy is set. at other times, it may cause data to be corrupted. also note that, if the fifo is double-buffered, flushfifo may need to be set twice to completely clear the fifo. 2 underrun r/w 0x0 the usb sets this bit to 1 if an in token is received when the txpktrdy bit not set. the cpu should clear this bit. downloaded from: http:///
95/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 txcsr in peripheral mode C continued bits name direction reset description 1 fifonotempty r/w 0x0 the usb sets this bit to 1 when there is at least 1 packet in the tx fifo. txpktrdy r/w 0x0 the cpu sets this bit to 1 after loading a data packet into the fifo. it is cleared automatically when the data packet has been transmitted. an interrupt is generated (if enabled) when the bit is cleared. txpktrdy is also automatically cleared prior to loading a second packet into a double-buffered fifo. 0 rxpktrdy r 0x0 this bit is set to 1 when a data packet has been received. an interrupt is generated when this bit is set. the cpu clears this bit by setting the servicedrxpktrdy bit. txcsr in host mode offset: 0x12 width: 16 bits bits name direction reset description 15 autoset r/w 0x0 when cpu sets this bit, txpktrdy will be automatically set when data of the maximum packet size (value in txmaxp) is loaded into the tx fifo. if a packet of less than the maximum packet size is loaded, then txpktrdy will have to be set manually. note: this bit should not be set for either high-bandwidth isochronous endpoints or high-bandwidth interrupt endpoints. 14 - r/w 0x0 unused, always returns 0 13 mode r/w 0x0 cpu sets this bit to 1 to enable the endpoint direction as tx, and clears it to enable the endpoint direction as rx. note: this bit only has any effect where the same endpoint fifo is used for both tx and rx transactions. 12 dmareqenab r/w 0x0 cpu sets this bit to 1 to enable the dma request for the tx endpoint. 11 frcdatatog r/w 0x0 cpu sets this bit to 1 to force the endpoint data toggle to switch and the data packet to be cleared from the fifo, regardless of whether an ack was received. this can be used by interrupt tx endpoints that are used to communicate rate feedback for isochronous endpoints. 10 dmareqmode r/w 0x0 the cpu sets this bit to 1 to select dma mode 1 and clears this bit to select dma mode 0. note: this bit must not be cleared either before or in the same cycle as the above dmareqenab bit is clear 9:8 C r 0x0 unused, always returns 0 7 nak timeout incomptx r/w 0x0 bulk endpoints only: this bit is set to 1 when the tx endpoint is halted following the receipt of nak responses for longer than the time set as the nak limit by the txinterval register. the cpu should clear this bit to allow the endpoint to continue. high-bandwidth interrupt endpoints only: this bit will be set if no response is received from the device to which the packet is being sent. 6 clrdatatog r/w 0x0 cpu sets this bit to 1 to reset the endpoint data toggle to 0. 5 sentstall r/w 0x0 this bit is set to 1 when a stall handshake is received. when this bit is 1, any dma request that is in progress is stopped, the fifo is completely flushed and the txpktrdy bit is cleared (see below). the cpu should clear this bit. downloaded from: http:///
96/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 txcsr in host mode C continued bits name direction reset description 4 C r 0x0 unused, returns 0 when read 3 flushfifo r/w 0x0 the cpu sets this bit 1 to flush the latest packet from the endpoint tx fifo. the fifo pointer is reset, the txpktrdy bit (below) is cleared and an interrupt is generated. this bit may be set simultaneously with txpktrdy to abort the packet that is currently being loaded into the fifo. note: flushfifo should only be used when txpktrdy is set. at other times, it may cause data to be corrupted. also note that, if the fifo is double-buffered, flushfifo may need to be set twice to completely clear the fifo. 2 error r/w 0x0 the usb sets this bit to 1 when 3 attempts have been made to send a packet and no handshake packet has been received. when this bit is 1, an interrupt is generated, txpktrdy is cleared and the fifo completely flushed. the cpu should clear this bit. valid only when the endpoint is operating in bulk or interrupt mode. 1 fifonotempty r/w 0x0 the usb sets this bit to 1 when there is at least 1 packet in the tx fifo. 0 txpktrdy r/w 0x0 cpu sets this bit to 1 after loading a data packet into the fifo. it is cleared automatically when a data packet has been transmitted. an interrupt is also generated at this point (if enabled). txpktrdy is also automatically cleared prior to loading a second packet into a double-buffered fifo. rxmaxp the rxmaxp register defines the maximum amount of data that can be transferred through the selected rx endpoint in a single operation. there is a rxmaxp register for each rx endpoint (except endpoint 0). offset: 0x14 width: 16 bits bits name direction reset description 15:11 - n/a 0x0 - 10:0 maximum payload/transa ction r/w 0x0 maximum payload/transaction downloaded from: http:///
97/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 rxcsr in peripheral mode offset: 0x16 width: 16 bits bits name direction reset description 15 autoclear r/w 0x0 when cpu sets this bit to 1, the rxpktrdy bit will be automatically cleared when a packet of rxmaxp bytes has been unloaded from the rx fifo. when packets of less than the maximum packet size are unloaded, rxpktrdy will have to be cleared manually. when using the dma to unload the rx fifo, data is read from the rx fifo in 4 byte chunks regardless of the rxmaxp. therefore, the rxpktrdy bit will be cleared as follows: remainder (rxmaxp/4) actual bytes read packet sizes that will clear rxpktrdy. 0 (i.e. rxmaxp = 64 bytes) rxmaxp rxmaxp, rxmaxp-1, rxmaxp-2, rxmaxp-3 3 (i.e. rxmaxp = 63 bytes) rxmaxp+1 rxmaxp, rxmaxp-1, rxmaxp-2 2 (i.e. rxmaxp = 62 bytes) rxmaxp+2 rxmaxp, rxmaxp-1 1 (i.e. rxmaxp = 61 bytes) rxmaxp+3 rxmaxp note: this bit should not be set for high-bandwidth isochronous endpoints. 14 iso r/w 0x0 cpu sets this bit to 1 to enable the rx endpoint for isochronous transfers, and clears it to enable the rx endpoint for bulk or interrupt transfers. 13 dmareqena b r/w 0x0 cpu sets this bit 1 to enable the dma request for the rx endpoint. 12 disnyet/ pid error r/w 0x0 bulk/interrupt transactions: the cpu sets this bit to 1 to disable the sending of nyet handshakes. when set, all successfully received rx packets are ack'd including at the point at which the fifo becomes full. note: this bit is only valid in high-speed mode, in which it should be set for all interrupt endpoints. iso transactions: the core sets this bit to 1 to indicate a pid error in the received packet. 11 dmareqmo de r/w 0x0 the cpu sets this bit to 1 to select dma mode 1 and clears this bit to select dma mode 0. note: this bit should not be cleared in the same cycle as rxpktrdy is cleared. 10:9 C r 0x0 unused, always returns 0. 8 incomprx r/w 0x0 this bit is set in a high-bandwidth isochronous/interrupt transfer if the packet in the rx fifo is incomplete because parts of the data were not received. it is cleared when rxpktrdy is cleared. note: in anything other than a high-bandwidth transfer, this bit will always return 0. 7 clrdatatog r/w 0x0 the cpu sets this bit to 1 to reset the endpoint data toggle to 0. 6 sentstall r/w 0x0 this bit is set to 1 when a stall handshake is transmitted. the cpu should clear this bit. downloaded from: http:///
98/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 rxcsr in peripheral mode C continued bits name direction reset description 5 sendstall r/w 0x0 the cpu sets this bit to 1 to issue a stall handshake. the cpu clears this bit to terminate the stall condition. note: (a) the fifo should be flushed before sendstall is set. (b) this bit has no effect when the endpoint is being used for isochronous transfers. 4 flushfifo r/w 0x0 the cpu sets this bit to 1 to flush the next packet to be read from the endpoint rx fifo. the fifo pointer is reset and the rxpktrdy bit (below) is cleared. note: flushfifo should only be used when rxpktrdy is set. at other times, it may cause data to be corrupted. also note that, if the fifo is double-buffered, flushfifo may need to be set twice to completely clear the fifo. 3 dataerror r 0x0 this bit is set to 1 if rxpktrdy is set when the data packet has a crc or bit-stuff error. it is cleared when rxpktrdy is cleared. note: this bit is only valid when the endpoint is operating in iso mode. in bulk mode, it always returns zero. 2 overrun r/w 0x0 this bit is set to 1 if an out packet cannot be loaded into the rx fifo. the cpu should clear this bit. note: this bit is only valid when the endpoint is operating in iso mode. in bulk mode, it always returns zero. 1 fifofull r 0x0 this bit is set to 1 when no more packets can be loaded into the rx fifo. 0 rxpktrdy r/w 0x0 this bit is set to 1 when a data packet has been received. the cpu should clear this bit when the packet has been unloaded from the rx fifo. an interrupt is generated when the bit is set. downloaded from: http:///
99/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 rxcsr in host mode offset: 0x16 width: 16 bits bits name direction reset description 15 autoclear r/w 0x0 when the cpu sets this bit to 1, the rxpktrdy bit will be automatically cleared when a packet of rxmaxp bytes has been unloaded from the rx fifo. when packets of less than the maximum packet size are unloaded, rxpktrdy will have to be cleared manually. when using the dma to unload the rx fifo, data is read from the rx fifo in 4 byte chunks regardless of the rxmaxp. therefore, the rxpktrdy bit will be cleared as follows: remainder (rxmaxp/4) actual bytes read packet sizes that will clear rxpktrdy. 0 (i.e. rxmaxp = 64 bytes) rxmaxp rxmaxp, rxmaxp-1, rxmaxp-2, rxmaxp-3 3 (i.e. rxmaxp = 63 bytes) rxmaxp+1 rxmaxp, rxmaxp-1, rxmaxp-2 2 (i.e. rxmaxp = 62 bytes) rxmaxp+2 rxmaxp, rxmaxp-1 1 (i.e. rxmaxp = 61 bytes) rxmaxp+3 rxmaxp note: this bit should not be set for high-bandwidth isochronous endpoints. 14 autoreq r/w 0x0 when cpu sets this bit to 1, the reqpkt bit will be automatically set when the rxpktrdy bit is cleared. note: this bit is automatically cleared when a short packet is received. 13 dmareqenab r/w 0x0 cpu sets this bit to 1 to enable the dma request for the rx endpoint. 12 disnyet/ pid error r 0x0 iso transactions only: the core sets this bit 1 to indicate a pid error in the received packet. bulk/interrupt transactions: this bit is disregarded. 11 dmareqmode r/w 0x0 the cpu sets this bit to select dma mode 1 and clears this bit to select dma mode 0. note: this bit should not be cleared in the same cycle as rxpktrdy is cleared. 10:9 C r 0x0 unused, always returns 0 8 incomprx r/w 0x0 this bit will be set in a high-bandwidth isochronous/interrupt transfer if the packet received is incomplete. it will be cleared when rxpktrdy is cleared. note: in anything other than a high-bandwidth transfer, this bit will always return 0. 7 clrdatatog r/w 0x0 cpu sets this bit to 1 to reset the endpoint data toggle to 0. 6 rxstall r/w 0x0 when a stall handshake is received, this bit is set to 1 and an interrupt is generated. the cpu should clear this bit. downloaded from: http:///
100/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 rxcsr in host mode C continued bits name direction reset description 5 reqpkt r/w 0x0 cpu sets this bit to 1 to request an in transaction. it is cleared when rxpktrdy is set. 4 flushfifo r/w 0x0 the cpu sets this bit to 1 to flush the next packet to be read from the endpoint rx fifo. the fifo pointer is reset and the rxpktrdy bit (below) is cleared. note: flushfifo should only be used when rxpktrdy is set. at other times, it may cause data to be corrupted. also note that, if the fifo is double-buffered, flushfifo may need to be set twice to completely clear the fifo. 3 dataerror/ nak timeout r/w 0x0 when operating in iso mode, this bit is set to 1 when rxpktrdy is set if the data packet has a crc or bit-stuff error and cleared when rxpktrdy is cleared. in bulk mode, this bit will be set to 1 when the rx endpoint is halted following the receipt of nak responses for longer than the time set as the nak limit by the rxinterval register. the cpu should clear this bit to allow the endpoint to continue. 2 error r/w 0x0 the usb sets this bit to 1 when 3 attempts have been made to receive a packet and no data packet has been received. the cpu should clear this bit. an interrupt is generated when the bit is set. note: this bit is only valid when the tx endpoint is operating in bulk or interrupt mode. in iso mode, it always returns zero. 1 fifofull r 0x0 this bit is set to 1 when no more packets can be loaded into the rx fifo. 0 rxpktrdy r/w 0x0 this bit is set to 1 when a data packet has been received. the cpu should clear this bit when the packet has been unloaded from the rx fifo. an interrupt is generated when the bit is set. rxcount rxcount is a 16-bit read-only register, which holds the number of received data bytes in the packet currently in line to be read from the rx fifo. if the packet was transmitted as multiple bulk packets, the number given will be for the combined packet. note: the value returned changes as the fifo is unloaded and is only valid while rxpktrdy (rxcsr.d0) is set. offset: 0x18 width: 16 bits bits name direction reset description 15:13 - n/a 0x0 - 12:0 endpoint rx count r 0x0 endpoint rx count txtype(host mode only) offset: 0x1a width: 6 bits bits name direction reset description 5:4 protocol r/w 2'h0 the cpu sets these bits to select the required protocol for the tx endpoint: 00: illegal 01: isochronous 10: bulk 11: interrupt 3:0 target endpoint number r/w 4'h0 the cpu should set this value to the endpoint number contained in the tx endpoint descriptor returned to the musbhdrc during device enumeration. downloaded from: http:///
101/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 txinterval (hos t mode only) txinterval is an 8-bit register that, for interrupt and isochronous transfers, defines the polling interval for the currently-selected tx endpoint. for bulk endpoints, this register sets the number of frames/microframes after which the endpoint should timeout on receiving a stream of nak responses . there is a txinterval register for each configured tx endpoint (except endpoint 0). offset: 0x1b width: 8 bits bits name direction reset description 7:0 tx polling interval/nak limit (m) r/w 8'h0 tx polling interval/nak limit (m) rxtype (host mode only) offset: 0x1a width: 6 bits bits name direction reset description 5:4 protocol r/w 2'h0 the cpu sets thest bits to select the required protocol for the rx endpoint: 00: illegal 01: isochronous 10: bulk 11: interrupt 3-0 target endpoint number r/w 4'h0 the cpu should set this value to the endpoint number contained in the rx endpoint descriptor returned to the musbhdrc during device enumeration. rxinterval (host mode only) rxinterval is an 8-bit register that, for interrupt and isochr onous transfers, defines the polling interval for the currently selected rx endpoint. for bulk endpoints, this register sets the number of frames/microframes after which the endpoint should timeout on receiving a stream of nak responses. there is a rxinterval register for each configured rx endpoint (except endpoint 0). offset: 0x1b width: 8 bits bits name direction reset description 7:0 rx polling interval/nak limit (m) r/w 8'h0 rx polling interval/nak limit (m) fifosize fifosize is an 8-bit register, which returns sizes of the fifos associated with the selected additional tx/rx endpoints. values of 3 C 13 correspond to a fifo size of 2n bytes (8 C 8192 bytes). if an endpoint has not been configured, a value of 0 will be displayed. when the tx and rx endpoints share the same fifo, the rx fifo size will be encoded as 0xf. offset: 0x1f width: 8 bits bits name direction reset description 7:4 rx fifo size r rx fifo size 3:0 tx fifo size r tx fifo size fifox this address range provides 16 addresses for cpu access to the fifos for each endpoint. writing to these addresses loads data into the tx fifo for the corresponding endpoint. re ading from these addresses unloads data from the rx fifo for the corresponding endpoint. offset:fifo0:0x20 fifo1:0x24 fifo2:0x28 fifo3:0x2c fifo4:0x30 width: 32 bits bits name direction reset description 31:0 fifox r/w fifox downloaded from: http:///
102/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 additional control & configuration registers (60h C 7fh) vcontrol (write only) utmi+ phy vendor register offset: 0x68 width: 16 bits bits name direction reset description 15:4 - - - reserved 3:0 vcontrol w vcontrol vstatus (read only) utmi+ phy vendor register offset: 0x68 width: 16 bits bits name direction reset description 15:8 - - - reserved 7:0 vstatus r vstatus dma registers address register direction reset description 200h intr r/w d0: indicates pending dma interrupts for channel 1 204h cntl (1) r/w dma channel 1 control: d0: enable dma d1: direction 0 = dma write (rx endpoint) 1 = dma read (tx endpoint) d2: dma mode d3: interrupt enable d7C4: endpoint number d8: bus error d10C9: burst mode 00 = burst mode 0 : bursts of unspecified length 01 = burst mode 1 : incr4 or unspecified length 10 = burst mode 2 : incr8, incr4 or unspecified length 11 = burst mode 3 : incr16, incr8, incr4 or unspecified length 208 addr (1) r/w dma channel 1 ahb memory address (32 bits) 20c count (1) r/w dma channel 1 byte count (32 bits) downloaded from: http:///
103/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 8.4. register (f8100000 usb connect detector) 8.4.1. memory map name offset r/w bit description connect 0xcc r/w 10 usb connection detection register hold dp dm line state at reset 0x0 power 0xd0 w 4 phy suspend control register at reset 0x0 utmisel 0x1400 w 6 utmi connection setting register at reset 0x0 usbtest 0x1404 w 1 usb test packet setting register reset 0x1 8.4.2. register detail usb connection detection register offset : 0xcc , reset : 0x0 bit name r/w reset description 9 linestate1_latch (dm) r x hold linestate1 (dm) value at the time of connection and disconnection detection 8 linestate0_latch (dp) r x hold linestate1 (dp) value at the time of connection and disconnection detection 7 discon_en _dm r/w 0x0 disconnection detection flag dm enable (clear at detection) 6 conn_en _dm r/w 0x0 connection detection flag dm enable (clear at detection) 5 discon_en _dp r/w 0x0 disconnection detection flag dp enable (clear at detection) 4 conn_en _dp r/w 0x0 connection detection flag dp enable (clear at detection) 3 linestate1 (dm) r x linestate[1] (dm) monitor 2 linestate0 (dp) r x linestate[0] (dp) monitor 1 discon_flg r/w 0x0 disconnection detection flag 0 conn_flg r/w 0x0 connection detection flag phy suspend control register offset : 0xd0 , reset : 0x0 bit name r/w reset description 15 regsw r/w 0x0 0: rstgen controls suspendm to phy 1: musbhdrc controls suspendm to phy 14:0 r/w 0x0 downloaded from: http:///
104/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 utmi connection setting register offset : 0x1400 , reset : 0x0 bit name r/w reset description 8 r/w 0x0 select musbhdrc's iddig input 0 a-type (normal) 1 b-type 7 r/w 0x0 select dmpulldown to phy 0 fix 1 (enable) 1 musbhdrc controls dmpulldown 6 r/w 0x0 select dppulldown to phy 0 fix 1 (enable) 1 musbhdrc controls dmpulldown 5 opmodesel r/w 0x0 0: normal connection 1: fix opmode[1:0] = 2'b01 please use this bit with a reset value. 4 rxvalidsel r/w 0x0 0 normal connection 1: only 1 pulse rise edge please use this bit with a reset value. 3 xcvrsel r/w 0x0 0 normal connection 1 xcvrsel[0] = 1 please use this bit with a reset value. 2 hostdiscon r/w 0x0 0 normal connection 1 hostdiscon = 0 please use this bit with a reset value. 1 rxerror r/w 0x0 0 normal connection 1 rxerror = 0 please use this bit with a reset value. 0 delay r/w 0x0 0 normal connection 1 rxactive,rxvalid,rxerror 1 cycle delay regading rxvalid, delay(bit0) select delay on/off to the signal selected by rxvalidsel (bit4) please use this bit with a reset value. usb test packet setting register offset : 0x1404 , reset : 0x0 bit name r/w reset description 0 usbtest r/w 0x0 0 normal connection 1 issue test packet downloaded from: http:///
105/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 9. sd i/f refer to another document [bm94081 kut sd i/f block datasheet] for the function of sd i/f block. downloaded from: http:///
106/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 10. quad spi i/f 10.1. features supports quad serial flash rom supports serial flash rom addresses up to 24 bits allows the control of control registers from the amba-ahb bus allows direct access from the memory map of the amba-ahb bus to serial flash rom includes 32-byte data transmit/receive fifos 10.2. description 10.2.1. block diagram the following section shows a quad serial flash controller block. ahb ahb bus i/f command address decoder control register spi fsm controller quad serial flash rom data fifo figure 42. quad serial flash controller block 10.2.2. connection the following section shows an example of connection with the quad serial flash rom. fl_dat0 fl_clk fl_dat3 fl_cs fl_dat1 fl_dat2 sio0 sclk sio3 cs# sio1 sio2 gnd vcc serial flash rom lsi figure 43. connection example downloaded from: http:///
107/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 10.2.3. command & address decoder in case of any access to the serial flash rom on the ahb memory map, the command & address decoder translates ahb address to serial flash rom address and to a command. the command uses a value set with the command id register. at this time, spi communication is automatically initiated. during data read to the serial flash rom is in progress, the ahb bus master is placed into a wait state waiting to be disabled. access from ahb supports single read/transfer of one word of 32 bits and burst read/transfer of eight words of 32 bits. 10.2.4. control register the control register allows access from the ahb bus to register s that are used to control the start/stop of spi communication, command setting, address setting, and communication setting. the register supports the width of ahb bus address and data up to 32 bits. 10.2.5. data fifo eight 32-bit data receive fifos are built in. eight 32-bit data transmit fifos are built-in. 10.2.6. spi format the spi format supports spi format mode0. this allows clock frequency setting from the format control register. the length of data frame is configurable in steps of 8 bits. figure 44. spi mode0 (rising clock edge: data latch, falling clock edge: data shift) 10.2.7. transfer modes single-spi mode single-spi mode allows simultaneous data transmit and receive. this mode is designed to exit upon completion of data transfer for the number of bytes set with the transmit data a mount setting and the receive data amount setting parameters. transmitted and received data are written and read by the s ndfifo and rcvfifo registers in the base address 0xf010_0000 area. the following diagram shows waveforms. figure 45. downloaded from: http:///
108/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 serial flash mode2 serial flash mode2 allows operation from data transmit through data receive. four data lines are used to execute serial communications. da t3 serves as the msb to execute 1-byte communication in two cycles. upon completion of data transfer for the number of bytes set with the transmit data amount setting paramete r, the data lines serve as input lines. upon completion of data transfer for the number of bytes set with the receive data amount setting parameter, this mode exits. in the command block, one data line (dat0) is used to execute communications in eight cycles. serial flash mode2 supports quad input / output fast_read (ebh) operation. received data are read by direct access to the base address 0x2000_0000 area. the following diagram shows waveforms. figure 46. 10.2.8. interrupt single-spi mode generates a cpu interrupt upon completion of data transfer for the set number of bytes. the interrupt signal polarity is low active. 10.3. i/o signals pin name i/o function destination sys_clk_i in ahb bus clock clkctr sfr_clk_i in serial flash clock clkctr rstb_i in reset (active low) rstgen fl_dat0 in/out serial flash data[0] pad fl_sclk out serial flash clock pad fldat3 in/out serial flash data[3] pad fl_cs out serial flash chip select pad fl_dat1 in/out serial flash data[1] pad fl_dat2 in/out serial flash data[2] pad hsel_ssfr_i in ahb hsel slave C serial flash rom direct ahb htrans_ ssfr _i in ahb htrans slave ahb hwrite_ ssfr _i in ahb hwrite data slave ahb hsize_ ssfr _i in ahb hsize slave ahb haddr_ ssfr _i in ahb haddr slave ahb hwdata_ ssfr _i in ahb hwdata slave ahb hready_ ssfr _i in ahb hreadyi slave ahb hready_ssfr_o out ahb hready out slave ahb hrdata_ssfr_o out ahb hrdata slave ahb hresp_ssfr_o out ahb responce slave ahb downloaded from: http:///
109/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 10.4. register 10.4.1. memory map name description address offset width reset control0 transfer control 0x00 16 16h0000 control1 format control 0x04 32 32h033e2000 sndbyte send byte number 0x08 8 8h10 rcvbyte received byte number 0x0c 8 8h10 status internal status 0x10 16 16h08a0 interrupt1 interrupt setting 1 0x14 8 8h00 interrupt2 interrupt setting 2 0x18 8 8hff interrupt3 interrupt monitor 0x1c 8 8hff sndfifo send fifo data 0x20 32 32h00000000 rcvfifo receive fifo data 0x24 32 32h00000000 fifocnt fifo control 0x28 32 32h00000000 commandid command id & dummy id 0x2c 32 32h0000eb00 10.4.2. register detail control0 transfer control offset: 0x00 width: 16 bits bits name direction reset description 15:8 r/w 0x0 - 7:4 r/w 0x0 transfer mode setting 0: - 1: - 2: single-spi transmit/receive 3: - 4: - 5: - 6: - 7: serial flash mode2 3 r/w - - 2 r/w 0x0 ahb direct access 0: disabled ahb direct access 1: enabled ahb direct access 1 r/w 0x0 - set 0 to this bit to write data. 0 r/w 0x0 spi start normally, 0 is read. writing 1 starts spi transfer. downloaded from: http:///
110/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 control1 format control offset: 0x04 width: 32 bits bits name direction reset description 21:28 r/w 0x0 - 27:24 r/w 0x3 sets the wait time after cs is activated until sclk starts up or after the last serial communication is completed before cs is deactivated. [3:0] *sclk 23:20 r/w 0x3 sets the wait time during serial transmit (8 bits). [3:0] *sclk 19:18 r/w 0x3 sets the fl_dat3 pin status in cs deactivated mode or in single-spi mode. 0, 1: input 2: low output 3: high output 17:16 r/w 0x2 sets the fl_dat2 pin status in cs deactivated mode or in single-spi mode. 0, 1: input 2: low output 3: high output 15:14 r/w 0x0 sets the fl_dat1 pin status in cs deactivated mode 0, 1: input 2: low output 3: high output 13:12 r/w 0x2 sets the fl_dat0 pin status in cs deactivated mode 0, 1: input 2: low output 3: high output 11 r/w 0x0 - 10 r/w 0x0 fixes cs output to low 9 r/w 0x0 fixes cs output to high 8 r/w 0x0 - set 0 to this bit to write data. 7 r/w 0x0 - set 0 to this bit to write data. 6 r/w 0x0 - set 0 to this bit to write data. 5 r/w 0x0 - set 0 to this bit to write data. 4 r/w 0x0 0: activates sclk output 1: deactivates sclk output 3:0 r/w 0x0 sclk frequency setting settlement of the transfer mode =2:single-spi mode 0x3 73.728mhz /8 0x4 73.728mhz /16 0x5 73.728mhz /32 0x6 73.728mhz /64 settlement of the transfer mode =7: serial flash mode2 0x0 73.728mhz/1 0x1 73.728mhz/2 0x2 73.728mhz /4 0x3 73.728mhz /8 0x4 73.728mhz /16 0x5 73.728mhz /32 0x6 73.728mhz /64 downloaded from: http:///
111/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 sndbyte offset: 0x08 width: 8 bits bits name direction reset description 5:0 r/w 0x10 transmitted data amount setting (in terms of bytes) data for the number of bytes set in this parameter is transmitted. the maximum set value is 32bytes. rcvbyte offset: 0x0c width: 8 bits bits name direction reset description 5:0 r/w 0x10 received data amount setting (in terms of bytes) data for the number of bytes set in this parameter is received. the maximum set value is 32bytes. status offset: 0x10 width: 16 bits bits name direction reset description 11 r 0x1 interrupt status at the end of transfer 10 r 0x0 - 9 r 0x0 - 8 r 0x0 - 7 r 0x1 internal receive fifo empty 6 r 0x0 internal receive fifo full 5 r 0x1 internal transmit fifo empty 4 r 0x0 internal transmit fifo full 3 r 0x0 - 2 r 0x0 - 1 r 0x0 spi transfer complete flag (this flag is cleared at transfer startup) 0 r 0x0 spi active flag interrupt1 offset: 0x14 width: 8 bits bits name direction reset description 7:1 r/w 0x0 - 0 r/w 0x0 clear spi transfer complete interrupt. 1: clear interrupt (one shot signal is set to high) 0 is read for readout. interrupt2 offset: 0x18 width: 8 bits bits name direction reset description 7:1 r/w 0x7f - 0 r/w 0x1 masks spi transfer co mplete interrupt. 0: not mask interrupt 1: mask interrupt downloaded from: http:///
112/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 interrupt3 offset: 0x1c width: 8 bits bits name direction reset description 7 r 0x1 quad serial flash controller interrupt status (status after masking is outputted) 0: interrupt generated 1: no interrupt generated 6:1 r 0x3f - 0 r 0x1 spi transfer complete interrupt status 0: interrupt generated 1: no interrupt generated sndfifo offset: 0x20 width: 32 bits bits name direction reset description 31:0 w 0x0 write data to transmit data fifo. rcvfifo offset: 0x24 width: 32 bits bits name direction reset description 31:0 r 0x0 read data from receive data fifo. fifocnt offset: 0x28 width: 24 bits bits name direction reset description 23:16 r 0x0 reads the number of data bytes saved in receive data fifo. 15:8 r 0x0 reads the number of data bytes saved in transmit data fifo. 7:2 r/w 0x0 - 1 r/w 0x0 clears receive data fifo. 0: normal fifo operation 1: clear the read pointer of receive data fifo 0 r/w 0x0 clears transmit data fifo. 0: normal fifo operation 1: clear the write pointer of transmit data fifo commandid offset: 0x2c width: 16 bits bits name direction reset description 15:8 r/w 0xeb sets the command id used for direct access to ahb or read command id for flash rom. 7:0 r/w 0x00 sets the command id used for direct access to ahb or dummy id used to read flash rom. the id is output by the msb fast method. downloaded from: http:///
113/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 11. ssi master 11.1. feature ? it is connected with the apb interface of the amba standard. ? the apb bus width is 32 bits. ? it operates as a master device. ? the mask of all the interrupt signals can be done. ? transmit fifo overflow interrupt ? transmit fifo underflow interrupt ? receive fifo overflow interrupt ? receive fifo underflow interrupt ? receive fifo full interrupt ? the depth of the first two fifo is 16 words at the transfer destination. the fifo data width is 16 bits. ? when data is transmitted, two slaves or less can be selected. ? a uniting interrupt signal is outputted with active low polarity. ? the serial protocol corresponds to motorola, inc. spi. ? the bit rate of the serial clock for the data transfer is controlled. ? the programmer can decide the size of sent and received data from 4 bits to 16 bits. ? ssi clk can be chosen from dividing the system clock (1-8 dividing frequency). (refer to the clockcontroller block). it has the dma handshake interface for transmission and reception. 11.2. description 11.2.1. serial protocol spi this is the serial protocol developed in motorola, inc. the rising edge of the clock can be selected. slave's selection signal is fixed to high when ssi is idle or if it is inactive. 11.2.2. clock ratio the frequency of the serial input clock should be less than or equal to the frequency of pclk. when ssi is a master device, the maximum frequency of bit rate clock (sclk_out) is 1/4 of the frequency of ssi_clk. figure 47. serial format downloaded from: http:///
114/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 11.3. i/o signal figure 48. ssi_m module ssi _ master pclk presetn psel paddr [ 7 0 ] pwdata [ 31 0 ] pwrite penable prdata [ 31 0 ] txd rxd ss _ in _ n dma _ tx _ req dma _ rx _ req dma _ tx _ single dma _ rx _ single dma _ tx _ ack dma _ tx _ ack ssi _ clk ssi _ rst _ n ssi _ oe _ n ssi _ sleep serial bus sclk_out ss _ 0 _ n serial master ssi _ intr _ n interrupt apb slave i/f dma i/f downloaded from: http:///
115/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 terminal list of ssi_m module terminal name i/o description connection pclk in apb clock clock gen presetn in apb reset reset gen psel in apb peripheral select signal apb paddr[7:0] in apb address apb pwdata[31:0] in apb write data apb pwrite in apb write signal apb penable in apb enable signal apb prdata[31:0] out apb read data apb ssi_clk in the serial clock clock gen ssi_rst_n in ssi module reset signal reset gen txd out transmission data the data transfer is done using this signal from the master to the slave. i/o rxd in reception data the data transfer is done using this signal from the master to the slave. i/o ss_in_n in the slave select signal (active low) the multi master system is fixed to high because it has no connection. "1" ssi_oe_n out output enable signal (active low) i/o ssi_sleep out ssi enable flag this signal becomes active when ssi is enabled. system clock generator/control module can disable the ssi_clk input. this reduces the power consumption of the system. 0:ssi is enabled. 1:ssi is disabled. open sclk_out out serial bit rate clock it is generated from ssi_clk by the ssi module. i/o ss_0_n out one slave select signal (active low for spi) i/o ssi_intr_n out ssi module interrupt flag of the individual interrupt signal ictl dma_tx_req out fifo dma transmission request this is effective when dma controller is needed. 0: there is no request. 1: there is a request. dmac dma_rx_req out fifo dma reception request this is effective when dma controller is needed. 0: there is no request. 1: there is a request. dmac dma_tx_single out fifo single dma transmission signal 0: fifo for the transmission is full. 1: fifo for the transmission is not full. dmac dma_rx_single out fifo single signal for the dma reception. 0: fifo for the reception is full. 1: fifo for the reception is not full. dmac dma_tx_ack in acknowledge for dma transmission dmac dma_rx_ack in acknowledge for dma reception dmac downloaded from: http:///
116/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 11.4. register 11.4.1. memory map name description address offset r/w width reset ctrlr0 control register 0 0x0 r/w 16 bits 0x00000007 ctrlr1 control register 1 0x4 r/w 16 bits 0x00000000 ssienr ssi enable register 0x8 r/w 1 bit 0x00000000 ser slave enable register 0x10 r/w 1 bit 0x00000000 baudr baud rate select 0x14 r/w 16 bits 0x00000000 txftlr transmit fifo threshold level 0x18 r/w 5 bits 0x00000000 rxftlr receive fifo threshold level 0x1c r/w 5 bits 0x00000000 txflr transmit fifo level register 0x20 r 5 bits 0x00000000 rxflr receive fifo level register 0x24 r 5 bits 0x00000000 sr status register 0x28 r 7 bits 0x00000006 imr interrupt mask register 0x2c r/w 6 bits 0x0000003f isr interrupt status register 0x30 r 6 bits 0x00000000 risr raw interrupt status register 0x34 r 6 bits 0x00000000 txoicr transmit fifo overflow interrupt clear register 0x38 r 1 bit 0x00000000 rxoicr receive fifo overflow interrupt clear register 0x3c r 1 bit 0x00000000 rxuicr receive fifo underflow interrupt clear register 0x40 r 1 bit 0x00000000 msticr multi-master interrupt clear register 0x44 r 1 bit 0x00000000 downloaded from: http:///
117/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 memory map C continued (note 1) width is given to the address so that the ahb address ma y do the increment at the burst access by ahb master like dma controller, and the memory map is prepared for 16 cycles in 32 bits or less width increment type burst, and addressoffset=0x60-0x9c. name description address offset r/w width reset icr interrupt clear register 0x48 r 1 bit 0x00000000 dmacr dma control register 0x4c r/w 2 bits 0x00000000 dmatdlr dma transmit data level 0x50 r/w 4 bits 0x00000000 dmardlr dma receive data level 0x54 r/w 4 bits 0x00000000 idr identification register 0x58 r 32 bits 0x00000000 ssi_comp _version core kit version id 0x5c r 32 bits 0x3332322a dr (note 1) data register 0x60-9c r/w 16 bits 0x00000000 downloaded from: http:///
118/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 11.4.2. register detail. ctrlr0 this register controls the serial data transfer. writing c annot be done to this register when ssi is enabled. writing can be done for the ssienr register by disabling the ssi. address offset : 0x0 bits name direction reset description 15:12 cfs r/w 0x0 (reserved) 11 srl r/w 0x0 shift register loop this is used during test. 0: normal mode 1: test mode txd is internally connected with rxd when changing to test mode consequently, sfit register loop can be tested 9:8 tmod r/w 0x0 transfer mode setting the transfer mode of the serial communication. it shows whether received data or the transmitted data is effective. transmission only mode receiving data from an external device is invalid, and is not stored in fifo for reception. it is rewritten by the next forwarding stage reception only mode transmission data is invalid. after writing in fifo for transmission, the data of the same word is sent again for the forwarding period. transmission & receiving mode both the transmission and the reception are effective. the data transfer continues until fifo for transmission empties. the data received from an external device is stored in receive fifo, and can be accessed from the host. 00 : transmission & reception 01 : transmissiononly 10 : receptiononly 11 : (reserved) 7:6 reserved and read as zero 5:4 frf r 0x0 frame format the protocol is set. 0. motorola, inc. spi * only motorola, inc. spi is supported in this device. 3:0 dfs r/w 0x7 setting of size of data frame the size of the frame in 16 bits or less can be set. 0000: reserved 0001: reserved 0010: reserved 0011: 4bit serial data transfer 0100: 5bit serial data transfer 0101: 6bit serial data transfer 0110: 7bit serial data transfer 0111: 8bit serial data transfer 1000: 9bit serial data transfer 1001: 10bit serial data transfer 1010: 11bit serial data transfer 1011: 12bit serial data transfer 1100: 13bit serial data transfer 1101: 14bit serial data transfer 1110: 15bit serial data transfer 1111: 16bit serial data transfer downloaded from: http:///
119/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 ctrlr1 this register becomes effective only when it is used as master device. the end of the serial transfer is controlled at receivin g only mode. this register cannot be set when ssi is enabled. address offset : 0x04 ssienr ssi is disabled or it is set as enable. address offset : 0x08 ser it is effective when ssi is a master device. it is possible to output it from the master to an individual slave. address offset : 0x10 baudr this register becomes effective only when it is used as master device. the frequency of the clock that does the data transfer is set. address offset : 0x14 txftlr the threshold of the fifo memory for the transmission is set. address offset : 0x18 rxftlr the threshold of the fifo memory for the reception is set. address offset : 0x1c bits name direction reset description 15:0 ndf r/w 0x0 the number of data frames is set. the number of data frames received by ssi is set at tmod=10 or tmod=11. it keeps receiving until the number of received data frames becomes the same number as this register +1. however, the maximum is 64kb. forwarding continues as long as the slave is selected at the slave device. bits name direction reset description 0 ssi_en r/w 0x0 ssi is enabled. all serial transfers interrupt at once. fifo is cleared. control register cannot be set when this is enabled. bits name direction reset description 0 ser r/w 0x0 slave select signal each bit deals with each slave. 0: not selected 1: selected bits name direction reset description 15: 0 sckdv r/w 0x0 the ratio of dividing frequency of the clock is set. lsb is set to "0" always (the ratio of dividing frequency is an even number from 4 to 65534). sclk_out output is "0x0", sclk_out = ssi_clk/sckdv bits name direction reset description 4: 0 tft r/w 0x0 the fifo threshold for the transmission. it is necessary to set the value smaller than the depth of fifo. the value that becomes the trigger of the interrupt output is set. bits name direction reset description 4: 0 rft r/w 0x0 the fifo threshold for the reception. it is necessary to set the value below the depth of fifo. the value that becomes the trigger of the interrupt output is set. downloaded from: http:///
120/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 txflr this register contains the number of valid data that can be stored in the fifo memory during transmission. address offset : 0x20 rxflr this register contains the number of valid data that can be stored in the fifo memory for the reception. address offset : 0x24 sr this register contains the state, the fifo status, and the sending and receiving error of the present forwarding. address offset : 0x28 bits name direction reset description 4: 0 txtfl r 0x0 quantity of data there is in fifo for the transmission. bits name direction reset description 4: 0 rxtfl r 0x0 quantity of data there is in fifo for the reception. bits name direction reset description 6 dcol r 0x0 data collision error only effective when using as a master device. when another master selects the device as a slave, ssi is set to "1" in the data transfer. it is cleared by reading. 0: no error 1:there is data collision error. 5 txe r 0x0 transfer error once transfer starts, this register is asserted when fifo for transfer is empty. this bit is only effective when used as a slave device. data from forwarding the previous state is sent again to the txd line. 0: no error 1:forwarding error. 4 rff r 0x0 fifo for reception is full. when fifo for the reception is filled, this bit is set. 0: not full 1: full 3 rfne r 0x0 fifo for reception is not full. when clear is done and at least one or more fifo for the reception has data or is empty fifo, this register is modified. 0:receive fifo is empty. 1:receive fifo is not empty. 2 tfe r 0x1 fifo for transmission is empty. this bit is set when transmit fifo is empty. when fifo has data, this bit is cleared. 0:transmit fifo is not empty. 1:transmit fifo is empty. 1 tfnf r 0x1 transmit fifo has data. when fifo is full or has data, it is set. 0:transmit fifo is full. 1:transmit fifo is not full. 0 busy r 0x0 the busy flag. this register is set during serial transfer. when ssi is disabled or idle, this register is cleared. downloaded from: http:///
121/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 imr the mask of all the interrupt signals can be done. the mstim bit becomes invalid when using it as a slave. after reset, the mask is not done as for the interrupt signal. address offset : 0x2c isr for the mask state, the generated interrupt is seen. address offset : 0x30 risr the generated interrupt is displayed. address offset : 0x34 bits name direction reset description 5 mstim r/w 0x1 the master transfer collision interrupt mask 0: mask 1: no mask 4 rxfim r/w 0x1 receive fifo full interrupt mask 0: mask 1: no mask 3 rxoim r/w 0x1 receive fifo overflow interrupt mask 0: mask 1: no mask 2 rxuim r/w 0x1 the fifo underflow interrupt mask for reception 0: mask 1: no mask 1 txoim r/w 0x1 the fifo overflow interrupt mask for transmission 0: mask 1: no mask 0 txeim r/w 0x1 the fifo empty interrupt mask for transmission 0: mask 1: no mask bits name direction reset description 5 mstis r 0x0 the master transfer collision interrupt 0: no interrupt 1: interrupt 4 rxfis r 0x0 receive fifo full interrupt 0: no interrupt 1: interrupt 3 rxois r 0x0 receive fifo overflow mask 0: no interrupt 1: interrupt 2 rxuis r 0x0 the fifo underflow interrupt for reception 0: no interrupt 1: interrupt 1 txois r 0x0 the fifo overflow interrupt for transmission 0: no interrupt 1: interrupt 0 txeis r 0x0 the fifo empty interrupt for transmission 0: no interrupt 1: interrupt bits name direction reset description 5 mstir r 0x0 the master transfer collision interrupt 0: no interrupt 1: interrupt 4 rxfir r 0x0 receive fifo full interrupt 0: no interrupt 1: interrupt 3 rxoir r 0x0 receive fifo overflow interrupt 0: no interrupt 1: interrupt 2 rxuir r 0x0 the fifo underflow interrupt for reception 0: no interrupt 1: interrupt 1 txoir r 0x0 the fifo overflow interrupt for transmission 0: no interrupt 1: interrupt 0 txeir r 0x0 the fifo empty interrupt for transmission 0: no interrupt 1: interrupt downloaded from: http:///
122/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 txoicr transmit fifo overflow interrupt clear register address offset : 0x38 rxoicr receive fifo overflow interrupt clear register address offset : 0x3c rxuicr receive fifo underflow interrupt clear register address offset : 0x40 msticr master collision interru pt clear register address offset : 0x44 icr all interrupt clear register address offset : 0x48 dmacr the dma control register. address offset : 0x4c dmatdlr the dma transmission data level address offset : 0x50 dmardlr the dma receive data level address offset : 0x54 bits name direction reset description 0 txoicr r 0x0 transmit fifo overflow interrupt clear register bits name direction reset description 0 rxoicr r 0x0 receive fifo overflow interrupt clear register bits name direction reset description 0 rxuicr r 0x0 receive fifo underflow interrupt clear register bits name direction reset description 0 msticr r 0x0 master collision interrupt clear register bits name direction reset description 0 icr r 0x0 all interrupt clear register bits name direction reset description 1 tdmae r/w 0x0 transmission dma is enabled. the dma channel is turned on and off with this bit. 0 :transmission dma is disabled. 1 :transmission dma is enabled. 0 rdmae r/w 0x0 reception dma is enabled. the dma channel is turned on and off with this bit. 0 :reception dma is disabled. 1 :reception dma is enabled. bits name direction reset description 3:0 dmatdl r r/w 0x0 the transmission data level timing in which the dma request output can be set. when becoming equal, the numbers of data collected in fifo output the dma_tx_req signal with the set value. bits name direction reset description 3:0 dmardlr r/w 0x0 the receive data level timing in which the dma request output can be set. when becoming equal, the data collected in fifo outputs the dma_rx_req signal with the set value. downloaded from: http:///
123/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 idr individual recognition code address offset : 0x58 ssi_comp_verion version of ssi address offset : 0x5c dr ssi has fifo with 16-bit width for transmission and re ception. the value of receive fifo can be read by accessing this register. when writing is finished, data is written in transmit fifo. it reads out data from the fifo, and it writ es it automatically on any address whether read or write. address offset : 0x60-0x9c bits name direction reset description 31: 0 idcode r - ssi module identification number bits name direction reset description 31: 0 ssi_comp_ version r - ssi module version management number bits name direction reset description 15: 0 dr rw 0x0 the data register when writing by right adjust, and reading it, writing is right adjust. downloaded from: http:///
124/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 12. ssi slave 12.1. feature ? it is connected with the apb interface of the amba standard. ? the width of the apb bus is 32 bits. ? it operates as a slave device. ? interrupt and masking are independently done. ? transmit fifo overflow interrupt ? transmit fifo underflow interrupt ? receive fifo overflow interrupt ? receive fifo underflow interrupt ? receive fifo full interrupt ? the depth of both transfer source and destination fifo is 16 words. the width of fifo data is 16 bits. ? the uniting interrupt signal is outputted, and the polarity of interrupt is active low. ? the serial protocol interface corresponds to motorola, inc. spi. ? the programmer can decide the size of the sent and received data from 4 bits to 16 bits. ? ssi_clk can be chosen from dividing the system clock (1-8 dividing frequency). (refer to the clock controller block.) ? it uses handshake for dma transmission and reception interface. 12.2. description 12.2.1. clock ration when the device functions as slave, the frequency of ssi_clk is needed to 16 times or more than the sclk_in clock. figure 49. sclk_out ssi_clk downloaded from: http:///
125/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 12.3. i/o signal figure 50. ssi _ slave pclk presetn psel paddr [ 7 0 ] pwdata [ 31 0 ] pwrite penable prdata [ 31 0 ] txd rxd ss _ in _ n dma _ tx _ req dma _ rx _ req dma _ tx _ single dma _ rx _ single dma _ tx _ ack dma _ tx _ ack ssi _ clk ssi _ rst _ n ssi _ oe _ n sclk_in ssi _ sleep serial bus serial slave ssi _ intr _ n interrupt apb slave i/f dma i/f downloaded from: http:///
126/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 terminal list of ssi slave module terminal name i/o description connection pclk in apb clock clock gen presetn in apb reset reset gen psel in in apb peripheral selection signal apb paddr[7:0] in apb address apb pwdata[31:0] in apb write data apb pwrite in apb write signal apb penable in apb enable signal apb prdata[31:0] out apb read data apb ssi_clk in the serial clock clock gen ssi_rst_n in ssi module reset signal reset gen txd out transmission data the data transfer is done using this signal from the master to the slave. i/o rxd in received data. the data transfer is done using this line from the master to the slave. i/o ss_in_n in slave select signal i/o ssi_oe_n out out enable signal (active low) i/o ssi_sleep out ssi enable flag this signal becomes active when ssi is enabled. system clock generator / control module can disable ssi_clkin. this reduces the power consumption of the system. 0: ssi is enable. 1: ssi is disabled. open sclk_in in serial bit rate clock out is done from the external master device. i/o ssi_intr_n out ssi module interrupt flag result of ored individual interrupt signals ictl dma_tx_req out fifo dma transmission request when this bit is set to 1, dma executes transmission request. 0: there is no request. 1: there is a request. dmac dma_rx_req out fifo dma reception request when this bit is set to 1, dma executes reception request. 0: there is no request. 1: there is a request. dmac dma_tx_single out fifo dma single transmission signal 0: fifo is not full for the transmission. 1: fifo is full for the transmission. dmac dma_rx_single out fifo dma single reception signal 0: fifo is not full for the reception. 1: fifo is full for the reception. dmac dma_tx_ack in acknowledge for dma transmission dmac dma_rx_ack in acknowledge for dma reception dmac downloaded from: http:///
127/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 12.4. register 12.4.1. memory map (note 1) width is given to the address so that the ahb addre ss may do the increment at the burst access by ahb master like dma controller, and the memory map is prepared for 16 cycles in 32bits or less width increment type burst, and addressoffset=0x60-0x9c. name description address offset r/w width reset ctrlr0 control register 0 0x0 r/w 16bits 0x00000007 ssienr ssi enable register 0x8 r/w 1bit 0x00000000 mwcr micro-wire control register 0xc r/w 3bits 0x00000000 txftlr transmit fifo threshold level 0x18 r/w 5bits 0x00000000 rxftlr receive fifo threshold level 0x1c r/w 5bits 0x00000000 txflr transmit fifo level register 0x20 r 5bits 0x00000000 rxflr receive fifo level register 0x24 r 5bits 0x00000000 sr status register 0x28 r 5bits 0x00000006 imr interrupt mask register 0x2c r/w 5bits 0x0000001f isr interrupt status register 0x30 r 5bits 0x00000000 risr raw interrupt status register 0x34 r 5bits 0x00000000 txoicr transmit fifo overflow interrupt clear register 0x38 r 1bit 0x00000000 rxoicr receive fifo overflow interrupt clear register 0x3c r 1bit 0x00000000 rxuicr receive fifo underflow interrupt clear register 0x40 r 1bit 0x00000000 msticr multi-master interrupt clear register 0x44 r 1bit 0x00000000 icr interrupt clear register 0x48 r 1bit 0x00000000 dmacr dma control register 0x4c r/w 2bits 0x00000000 dmatdlr dma transmit data level 0x50 r/w 4bits 0x00000000 dmardlr dma receive data level 0x54 r/w 4bits 0x00000000 idr identification register 0x58 r 32bits 0x00000000 ssi_com p_versio n core kit version id 0x5c r 32bits 0x33302322a dr (note 1) data register 0x60-9c r/w 16bits 0x00000000 downloaded from: http:///
128/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 12.4.2. register detail ctrlr0 this register controls the serial data transfer. writing c annot be done to this register when ssi is enabled. writing can be enabled for the ssienr register by disabling ssi.address offset : 0x00 bits name direction reset description 15:12 cfs r/w 0x0 (reserved) 11 srl r/w 0x0 shift register loop test 0: normal mode 1: test mode txd is connected with rxd internally when changing to the test mode, and loop can test. 10 slv_oe r/w 0x0 slave output enable this bit is only valid when device is operating as slave. ssi_oe_nout is set from slave's ssi.ssi_oe_nout doesn't actively become it for "1". in ssi_oe_n, it connects with tri-state i/o, and when this bit is "1", it is in high impedance state. it returns successful when the master does the data transfer to all slaves. after reset, it is necessary to disable this bit with software to be enabled, and to make the device work. 0 : slave txd is enabled. 1 : slave txd is disabled. 9:8 tmod r/w 0x0 transfer mode these bits dictate the transfer mode of the serial communication. these bits show data reception or data transmission is taking place. transmission only mode data reception from an external device is invalid. data are not stored in receive fifo and are rewritten on the next transfer. reception only mode data transmission is invalid. after writing in the transmit fifo, the data of the same word is sent again for the next transfer period. transmission & reception mode both data transmission and reception are valid. the data transfer continues until transmit fifo empties. the data received from an external device is stored in receive fifo, and can be accessed from the host. 00 : transmission & reception 01 : transmission only 10 : reception only 11 : (reserved) downloaded from: http:///
129/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 ctrlr0 C continued ssienr ssi is disabled or enabled. address offset : 0x08 txftlr txftlr sets the threshold of the fifo memory for transmission. address offset : 0x18 rxftlr rxftlr sets the threshold of the fifo memory for reception. address offset : 0x1c bits name direction reset description 7 scpol r 0x0 serial clock polarity this bit is only valid when device is using spi protocol. this bit sets the serial clock polarity of level data transfer. 0: stopping of level data transfer low 1 : stopping of level data transfer high 6 scph r 0x0 serial clock phase this bit is only valid when device is using spi protocol. 0: data is taken from the first edge of the serial clock. 1: the serial clock begins a one-cycle toggle after ssi slave line is enabled. data is taken on the following clock cycle. 5:4 frf r 0x0 frame format these bits set the protocol to be used. 00 : motorola, inc. spi *this device only supports motorola, inc. spi. 3:0 dfs r/w 0x7 data frame size the size of the frame can be set to 16 bits or less. 0000: reserved 0001: reserved 0010: reserved 0011: 4-bit serial data transfer 0100: 5-bit serial data transfer 0101: 6-bit serial data transfer 0110: 7-bit serial data transfer 0111: 8-bit serial data transfer 1000: 9-bit serial data transfer 1001: 10-bit serial data transfer 1010: 11-bit serial data transfer 1011: 12-bit serial data transfer 1100: 13-bit serial data transfer 1101: 14-bit serial data transfer 1110: 15-bit serial data transfer 1111: 16-bit serial data transfer bits name direction reset description 0 ssi_en r/w 0x0 ssi enable signal all serial transfers interrupt at once. fifo is cleared. the control register cannot be set when this signal is enabled. bits name direction reset description 4: 0 tft r/w 0x0 fifo threshold for transmission it is necessary to set this value less than the depth of fifo. this sets the value to trigger the interrupt. bits name direction reset description 4: 0 rft r/w 0x0 fifo threshold for reception it is necessary to set this value less than the depth of fifo. this sets the value to trigger the interrupt. downloaded from: http:///
130/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 txflr txflr indicates how much valid data are to be stored in the fifo memory for transmission. address offset : 0x20 rxflr rxflr indicates how much valid data are to be stored in the fifo memory for reception. address offset : 0x24 sr status register tells the current fifo status of the ongoing transfer transaction. address offset : 0x28 imr masking of all the interrupt signals can be done. the mstim bit becomes invalid when device operates as a slave. after reset, masking is not done on the interrupt signal. address offset : 0x2c bits name direction reset description 4: 0 txtfl r 0x0 available data in fifo for transmission bits name direction reset description 4: 0 rxtfl r 0x0 available data in fifo for reception bits name direction reset description 5 txe r 0x0 transfer error when transfer starts, this bit is set to 1 when transfer fifo is empty. this bit is only used when device operates as slave. data from previous transfer transaction is sent again to the transmission line. 0: no error 1 :transfer error occured. 4 rff r 0x0 receive fifo is full. this bit is set to 1 when fifo for reception is full. 0: not full 1: full 3 rfne r 0x0 receive fifo is not empty. this bit is set to 1 when at least one reception of fifo is not emptied, after clear is executed.0: receive fifo is empty. 1: receptio nfifo is not empty. 2 tfe r 0x1 transmit fifo is empty. this bit is set to 1 when transmit fifo is empty. when transmit fifo is not empty, this bit is cleared. 0: transmit fifo is not empty. 1: transmit fifo is empty. 1 tfnf r 0x1 transmit fifo is not full. this bit is set to 1 when transmit fifo is not full. 0: transmit fifo is full. 1: transmit fifo is not full. 0 busy r 0x0 busy flag this bit is set to 1 when there is an ongoing serial transfer. it is cleared at idle mode, when ssi is disabled. bits name direction reset description 4 rxfim r/w 0x1 receive fifo full interrupt mask 0: masking enabled 1: masking disabled 3 rxoim r/w 0x1 receive fifo overflow interrupt mask 0: masking enabled 1: masking disabled 2 rxuim r/w 0x1 receive fifo underflow interrupt mask 0: masking enabled 1: masking disabled 1 txoim r/w 0x1 transmit fifo overflow interrupt mask0: masking enabled 1: masking disabled 0 txeim r/w 0x1 transmit fifo empty interrupt mask 0: masking enabled 1: masking disabled downloaded from: http:///
131/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 isr generated interrupts during masking address offset : 0x30 risr risr displays the generated interrupts. address offset : 0x34 txoicr transmit fifo overflow interrupt clear register address offset : 0x38 rxoicr receive fifo overflow interrupt clear register address offset : 0x3c rxuicr receive fifo underflow interrupt clear register address offset : 0x40 msticr master collision interrupt clear register address offset : 0x44 bits name direction reset description 4 rxfis r 0x0 receive fifo full interrupt mask 0: interrupt disabled 1: interrupt enabled 3 rxois r 0x0 receive fifo overflow interrupt mask 0: interrupt disabled 1: interrupt enabled 2 rxuis r 0x0 receive fifo underflow interrupt mask 0: interrupt disabled 1: interrupt enabled 1 txois r 0x0 transmit fifo overflow interrupt mask 0: interrupt disabled 1: interrupt enabled 0 txeis r 0x0 transmit fifo empty interrupt mask 0: interrupt disabled 1: interrupt enabled bits name direction reset description 4 rxfir r 0x0 receive fifo full interrupt mask 0: interrupt disabled 1: interrupt enabled 3 rxoir r 0x0 receive fifo overflow interrupt mask 0: interrupt disabled 1: interrupt enabled 2 rxuir r 0x0 receive fifo underflow interrupt mask 0: interrupt disabled 1: interrupt enabled 1 txoir r 0x0 transmit fifo overflow interrupt mask 0: interrupt disabled 1: interrupt enabled 0 txeir r 0x0 transmit fifo empty interrupt mask 0: interrupt disabled 1: interrupt enabled bits name direction reset description 0 txoicr r 0x0 transmit fifo overflow interrupt clear register bits name direction reset description 0 rxdicr r 0x0 receive fifo overflow interrupt clear register bits name direction reset description 0 rxuicr r 0x0 receive fifo underflow interrupt clear register bits name direction reset description 0 msticr r 0x0 master collision interrupt clear register downloaded from: http:///
132/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 icr all interrupt clear register address offset : 0x48 dmacr dma control register address offset : 0x4c dmatdlr dma transmission data level address offset : 0x50 dmardlr dma reception data level address offset : 0x54 idr individual recognition code address offset : 0x58 ssi_comp_verion ssi version address offset : 0x5c dr ssi has a 16-bit fifo for transmission and reception. the value of the receive fifo can be read by accessing this register. when writing is done, data is written in the transmission either writing or reading is possible in any address. address offset : 0x60-0x9c bits name direction reset description 0 icr r 0x0 all interrupt clear register bits name direction reset description 1 tdmae r/w 0x0 dma transmission enable this bit enables data transmission in dma channel. 0: dma transmission is disabled. 1: dma transmission is enabled. 0 rdmae r/w 0x0 dma reception enable this bit enables data reception in dma channel. 0: dma reception is disabled. 1: dma reception is enabled. bits name direction reset description 3:0 dmatdlr r/w 0x0 dma transmission data level this register sets the timing in which dma request is executed. when dma_tx_req is set, it dictates the number of collected fifo data to be outputted. bits name direction reset description 3:0 dmardlr r/w 0x0 the reception data level this register sets the timing in which dma request is executed. when dma_rx_req is set, it dictates the number of collected fifo data to be read. bits name direction reset description 31: 0 idcode r - ssi module identification number bits name direction reset description 31: 0 ssi_com p_versi on r - ssi module version management number bits name direction res et description 15: 0 dr rw 0x0 data register when writing or reading, operation starts from the right. downloaded from: http:///
133/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 13. i2c0/i2c1 13.1. feature ? i2c serial interface. ? two speed modes are supported. ? standard mode (100kb/s) ? fast mode (400kb/s) ? the master slave i2c operation is supported. ? 7-bit slave address in a 10-bit packet format in both modes. ? 32-steps fifo is built-in for transmission and for reception. ? dma handshake interface. 13.2. description 13.2.1. i2c protocol start condition and stop condition protocol the i2c protocol of dw_apb_i2c is shown below figure 51: figure 51. dw_apb_i2c start and stop condition when the i2c bus is idle, sda and scl becomes h due to a pull-up resistance set externally. when the communication begins, during scl is h, sda transitions from h to l in the master side (start condition). when the communication ends, during scl is h, sda transitions from l to h in the master side (stop condition). when scl is l, the data is transferred inside for every change in sda. downloaded from: http:///
134/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 i2c protocol C continued ? protocol in slave address 7-bit slave address in a 10-bit packet format in both modes is shown. moreover, a special 10-bit slave address packet format is shown in the following table. figure 52. 7-bit address format figure 53. 10-bit address format i 2 c definition of bits in first byte slave address r/w bit description 000_0000 0 general call address 000_0000 1 start byte: the slave doesn't have the ack response. 000_0001 x cbus address: the i2c module ignores this access. 000_0010 x reserved 000_0011 x reserved 000_01xx x high-speed master code 111_11xx x reserved 111_10xx x 10-bit slave addressing (refer to figure 52.) downloaded from: http:///
135/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 ? sending and receiving protocol sending and receiving protocol is shown. figure 54. master-transmitter protocol figure 55. master-receiver protocol downloaded from: http:///
136/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 ? start byte forwarding protocol start byte forwarding protocol is shown in figure 56. start byte forwarding is done according to the foll owing procedures. master generates start condition(s). master forwards start byte (0000_0001). master generates the ack clock pulse. there should be no response from the slave. (sda=h) master generates repeated start condition(sr). figure 56. start byte transfer 13.2.2. arbitration and clock generation ? clock synchronization the synchronization of the clock is done by controlling scl from l to h or from h to l using the device with the shortest h period or the device with the longest l period. this is for the case where two or more master is controlling the i2c bus to generate the scl clock during data transfer. ? arbitration two or more master controlling the i2c bus for data transfer at the same time can happen. because the transmission level does not correspond to the level of the bus when two or more master sends signal to sda line during transmission, the data becomes erroneous. as a result, the sda line should be mediated (arbitration). downloaded from: http:///
137/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 13.2.3. operation mode slave mode operation ? initialization the ic_enable register is adjusted to 0. the slave address is set to the ic_sar register. a required setting for the ic_con register is done. the ic_enable register is adjusted to one. ? data transmission operati on procedure(slave-transmitter) a corresponding address to ic_sar from the master is forwarded. the address and the direction of forwarding are determined by a recognized response. the rd_req interrupt is generated, and scl is made l. the tx_abrt interrupt is generated when data has remained in tx_fifo before reading. the data in the tx_fifo is then deleted. data is written in the ic_data_cmd register. (the cmd bit is 0 always. ) rd_req and tx_abrt interrupt are cleared. scl is active, and byte data is transmitted. master opens the i2c bus by holding the stop condition or in restart condition. ? data reception operation procedure (slave-receiver) a corresponding address to ic_sar from master is forwarded. the address and the direction of forwarding are determined by a recognized response. data is stored during reception in the reception buffer. status and interrupt bit of the reception buffer are updated. the ic_data_cmd register is read. master opens the i2c bus by holding the stop condition or in restart condition. ? bulk transfer after the first reading is requested, the data of multiple byte packets can be written in tx_fifo when it is recognized that the master device requested data reception of multiple byte packets. as a result, rd_req interrupts scl during the requested reading since the second byte becomes un necessary. when the number of demand bytes from master is less than the number of databytes written in tx_fifo, the data that remains in tx_fifo is cleared. downloaded from: http:///
138/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 mastering mode operation ? initialization the ic_enable register is adjusted to 0. the slave address is set to the ic_sar register. (if necessary ) a setting for the ic_con register is done. the address of the slave device that becomes an object is written in the ic_tar register, or the start byte and the general call address are set. the ic_enable register is adjusted to one. this is written in the ic_data_cmd register. ? data sending and receiving operation the cmd bit is written when data transmission is done and 0 byte data is written. when data reception is done, one is written in the cmd bit. at this time, the data byte is ignored. when data is transmitted, status and the interrupt signal of the transmission buffer and the reception buffer are updated. ? clock frequency setting default setting is 109 khz in standard speed mode and 484khz in fast speed mode. in master mode, it is necessary to set the following registers to an appropriate value. ic_ss_scl_lcnt is used for the maintenance period in idle state of the bus. secure first the bus line when using it from this state. standard speed mode setting example (99khz) offset register value description 0x14 ic_ss_scl_hcnt 0x1b7 (439) 0x180 ( 384= 96mhz x 4.0us) 0x18 ic_ss_scl_lcnt 0x203 (515) 0x1c4 ( 452= 96mhz x 4.7us ) fast speed mode setting example (396khz) offset register value description 0x1c ic_fs_scl_hcnt 0x4b (75) 0x3a ( 58= 96mhz x 0.6us ) 0x20 ic_fs_scl_lcnt 0x9f (159) 0x7d ( 125= 96mhz x 1.3us ) figure 57. generated scl downloaded from: http:///
139/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 13.2.4. spike control a separate internal counter is installed in scl and sda, the number of clock pulses is counted, and the signal is taken at any value of ic_*_spklen. this is the function to filter the spike of scl and sda. it is shown in figure 58. figure 58. spike filter example downloaded from: http:///
140/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 13.3. i/o signal i2c_scl ic_clk_oe ic_clk_in_a i2c_sda ic_data_oe ic_data_in_a downloaded from: http:///
141/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 terminal name i/o description connection pclk in apb clock clock gen presetn in apb reset reset gen psel in apb peripheral select signal apb paddr[7:0] in apb address apb pwdata[31:0] in apb write data apb pwrite in apb write signal apb penable in apb enable signal apb prdata[31:0] out apb read data apb ic_clk in the source clock for i2c clock gen ic_clk_in_a in i2c forwarding clock scl (asynchronous system) i/o ic_data_in_a in data for i2c (asynchronous system). i/o ic_rst_in in reset for i2c reset gen ic_clk_oe out i2c forwarding clock scl i/o ic_data_oe out data out for i2c i/o ic_en out i2c interface enable signal output open ic_intr_n out the interrupt signal intr debug_* out the debug signal open dma_tx_req out dma request for transmit fifo dma dma_rx_req out dma request for receive fifo dma dma_tx_single out transmit fifo status signal dma dma_rx_single out receive fifo status signal dma dma_tx_ack in dma transmission ack dma dma_rx_ack in dma reception ack dma downloaded from: http:///
142/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 13.4. register 13.4.1. memory map the composition of the memory map is shown below. mode master mode(m) slave mode(s) name offset r/w width mode description ic_con 0x00 r/w 7 m/s i2c control register initial value 0x0000_007d (def ic_slave_disable, ic_restart_en, ic_10bitaddr_master, ic_10bitaddr_slave, ic_max_speed_mode, ic_master_mode) ic_tar 0x04 r/w 12 m i2c target address register initial value 0x0000_0855 (def ic_10bitaddr_master 0 0 ic_default_tar_slave_addr) ic_sar 0x08 r/w 10 s i2c slave address register initial value 0x0000_0055 (def ic_default_slave_addr) ic_data_cmd 0x10 r/w 8(r) 9(w) m/s i2c sending and receiving data buffer & command register initial value 0x0000_0000 ic_ss_scl _hcnt 0x14 r/w 16 m during standard speed mode scl clock h section setting register initial value 0x0000_0190 (def ic_ss_scl_high_count) ic_ss_scl _lcnt 0x18 r/w 16 m during standard speed mode scl clock l section setting register initial value 0x0000_01d6 (def ic_ss_scl_low_count) ic_fs_scl _hcnt 0x1c r/w 16 m during fast speed mode scl clock h section setting register initial value 0x0000_003c (def ic_fs_scl_high_count) ic_fs_scl _lcnt 0x20 r/w 16 m during fast speed mode scl clock l section setting register initial value 0x0000_0082 (def ic_fs_scl_low_count) ic_intr_stat 0x2c r 12 m/s i2c interrupt status register initial value 0x0000_0000 ic_intr_mask 0x30 r/w 12 m/s i2c interrupt mask register initial value 0x0000_08ff ic_raw_intr _stat 0x34 r 12 m/s i2c interrupt status register initial value 0x0000_0000 ic_rx_tl 0x38 r/w 8 m/s i2c receive fifo status hold register initial value 0x0000_0000 (def ic_rx_tl) ic_tx_tl 0x3c r/w 8 m/s i2c transmit fifo status hold register initial value 0x0000_0000 (def ic_tx_tl) ic_clr_intr 0x40 r 1 m/s all interrupt clear register initial value 0x0000_0000 ic_clr_rx _under 0x44 r 1 m/s reception under interrupt clear register initial value 0x0000_0000 ic_clr_rx _over 0x48 r 1 m/s reception over interrupt clear register initial value 0x0000_0000 ic_clr_tx _over 04c r 1 m/s transmission over interrupt clear register initial value 0x0000_0000 ic_clr_rd_req 0x50 r 1 s reading request interrupt clear register initial value 0x0000_0000 downloaded from: http:///
143/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 memory map C continued name offset r/w width mode description ic_clr_tx _abrt 0x5 r 1 m/s transmission abort interrupt clear register initial value 0x0000_0000 ic_clr_rx _done 0x58 r 1 s reception completion interrupt clear register initial value 0x0000_0000 ic_clr _activity 0x5c r 1 m/s activity interrupt clear register initial value 0x0000_0000 ic_clr stop_det 0x60 r 1 m/s stop detection interrupt clear register initial value 0x0000_0000 ic_clr start_det 0x64 r 1 m/s start detection interrupt clear register initial value 0x0000_0000 ic_clr gencall 0x68 r 1 s gen_call interrupt clear register initial value 0x0000_0000 ic_enable 0x6c r/w 2 m/s i2c enable register initial value 0x0000_0000 ic_status 0x70 r 7 m/s i2c status register initial value 0x0000_0006 ic_txflr 0x74 r 6 m/s transmit fifo level register initial value 0x0000_0000 ic_rxflr 0x78 r 6 m/s receive fifo level register initial value 0x0000_0000 ic_sda_hold 0x7c r/w 16 length setting of sda hold time register initial value 0x0000_0001 ic_tx_abrt _source 0x80 r/w 32 m/s i2c transmission abort status register initial value 0x0000_0000 ic_dma_cr 0x88 r/w 2 m/s the control register for dma handshake interface for sending and receiving initial value 0x0000_0000 ic_dma_tdlr 0x8c r/w 5 m/s the fifo threshold register for transmission initial value 0x0000_0000 ic_dma_rdlr 0x90 r/w 5 m/s the fifo threshold register for reception initial value 0x0000_0000 ic_sda_setup 0x94 r/w 8 i2c sda setup register initial value:0x0000_0064 ic_ack_genera l_call 0x98 r/w 1 i2c general call ack response setting register initial value:0x0000_0001 ic_enable_stat us 0x9c r 3 i2c enable status register initial value 0x0000_0000 ic_fs_spklen 0xa0 r/w 8 standard/fast mode spike control limit value initial value 0x0000_0001 downloaded from: http:///
144/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 13.4.2. register detail. detailed content of the register is shown below. ic_con (it is possible to set it only at ic_enable=0. ) i2c control register. this register is writable only in i2c disabled state (ic_enable=0). address offset : 0x00 bits name r/w default mode description 31:7 reserved n/a - - - 6 ic_slave_disable r/w 0 0: the slave function is enabled 1: slave function disabled 5 ic_restart_en r/w 1 m 1: restart transmission is possible 4 ic_10bitaddr_master r/w 1 m address mode setting 0: 7 bits 1: 10 bits 3 ic_10bitaddr_slave r/w 1 s address mode setting 0: 7 bits 1: 10 bits 2:1 ic_max_speed_mode r/w 0x2 m speed mode setting 0: no permission (fast speed mode) 1: standard speed mode 2:fast speed mode 3: fast speed mode (not connected to high speed mode) 0 ic_master_mode r/w 1 0: master function disabled 1: master function is enabled ic_tar (it is possible to set it only at ic_enable=0. ) target address setting register. this register is wr itable only in i2c disabled state (ic_enable=0). address offset : 0x04 bits name r/w default description 31:12 reserved n/a - - 11 special r/w 0 1: i2c special command execution set by gc_or_start bit 10 gc_or_start r/w 0 0: general call address 1: start byte 9:0 ic_tar r/w 0x055 target address ic_sar (it is possible to set it only at ic_enable=0. ) slave address setting register. this register is writable only in i2c disabled state (ic_enable=0). address offset : 0x08 bits name r/w default description 31:10 reserved n/a - - 9:0 ic_sar r/w 0x055 slave address ic_data_cmd the i2c data transfer register address offset : 0x10 bits name r/w default description 31:9 reserved n/a - - 8 cmd r/w 0 0 during write: transmission setting 1: 0 during read 7:0 dat r/w 0x00 i2c bus sending and receiving data ic_ss_scl_hcnt (it is possible to set it only at ic_enable=0. ) setting for high pulse width of scl during i2c standard speed mode address offset : 0x14 bits name r/w default description 31:16 reserved n/a - - 15:0 ic_ss_scl_hcnt r/w 0x0190 minimum value of scl clock h section at standard mode: 6 ic_ss_scl_lcnt (it is possible to set it only at ic_enable=0. ) setting for low pulse width of scl during i2c standard speed mode address offset : 0x18 bits name r/w default description 31:16 reserved n/a - - 15:0 ic_ss_scl_lcnt r/w 0x01d6 scl clock l section at standard mode minimum value 8 downloaded from: http:///
145/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 ic_fs_scl_hcnt (it is possible to set it only at ic_enable=0. ) setting for high pulse width of scl during i2c fast speed mode address offset : 0x1c bits name r/w default description 31:16 reserved n/a - - 15:0 ic_fs_scl_hcnt r/w 0x003c scl clock h section during fast mode minimum value 6 ic_fs_scl_lcnt (it is possible to set it only at ic_enable=0. ) setting for low pulse width of scl during i2c fast speed mode address offset : 0x20 bits name r/w default description 31:16 reserved n/a - - 15:0 ic_fs_scl_lcnt r/w 0x0082 scl clock l section during fast mode minimum value 8 ic_intr_stat during interrupt mask state, the generated interrupt is updated in this register. address offset : 0x2c bits name r/w default description 31:12 reserved n/a - - 11 r_gen_call r 0 general call request interrupt 0: no reception 1: general call request in reception 10 r_start_det r 0 begin of transmission interrupt 0: no start condition 1: start condition detected 9 r_stop_det r 0 end of transmission interrupt when the stop condition is detected by the i2c protocol, it is set. 0: no stop condition 1: stop condition detected 8 r_activity r 0 interrupt during transmission this register is set during i2c transmission. value remains until it is possible to clear from the idle state. reset condition: ? i2c error. ? ic_clr_activity register read ? ic_clr_intr register read ? system reset 0: no transmission 1: initial transmission during i2c activity 7 r_rx_done r 0 reception complete interrupt when there is nack from the i2c master during transmission, this bit is set. 0: incomplete reception 1: complete reception 6 r_tx_abrt r 0 transmission abort interrupt the transmission abort occurs when there is nack after first byte is transmitted (i2c master mode). refer to ic_tx_abrt_source for the set condition. 0: no abort 1: transmission abort 5 r_rd_req r 0 reception request interrupt this register is set when there is reception request (read) from other i2c masters in i2c slave mode. (the i2c bus maintains its value until it is changed to waiting state ) 0: no request 1: read request 4 r_tx_empty r 0 empty transmission buffer interrupt 0: transmission buffer level > ic_tx_tl 1: transmission buffer level ic_tx_tl 3 r_tx_over r 0 transmission buffer overflow interrupt 0: no overflow. downloaded from: http:///
146/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 bits name r/w default description 1: transmission buffer overflow 2 r_rx_full r 0 reception buffer full interrupt 0: reception buffer level ic_rx_tx 1: reception buffer level > ic_rx_tl 1 r_rx_over r 0 reception buffer overflow interrupt 0: no overflow. 1: reception buffer overflow 0 r_rx_under r 0 reception buffer underflow interrupt set when the reception buffer level = 0. read ic_data_cmd register ic_intr_mask the interrupt mask register write 0 to mask the interrupt address offset : 0x30 bits name r/w default description 31:12 reserved n/a - - 11 m_gen_call r/w 1 general call demand interrupt mask 0: mask interrupt 1: mask none 10 m_start_det r/w 0 start transmission interrupt mask 0: mask interrupt 1: mask none 9 m_stop_det r/w 0 end transmission interrupt mask 0: mask interrupt 1: mask none 8 m_activity r/w 0 interrupt mask during transmission 0: mask interrupt 1: mask none 7 m_rx_done r/w 1 reception completion interrupt mask 0: mask interrupt 1: mask none 6 m_tx_abrt r/w 1 transmission abort interrupt mask 0: mask interrupt 1: mask none 5 m_rd_req r/w 1 reception request interrupt mask 0: mask interrupt 1: mask none 4 m_tx_empty r/w 1 transmission buffer empty interrupt mask 0: mask interrupt 1: mask none 3 m_tx_over r/w 1 transmission buffer overflow interrupt mask 0: mask interrupt 1: mask none 2 m_rx_full r/w 1 reception buffer full interrupt mask 0: mask interrupt 1: mask none 1 m_rx_over r/w 1 reception buffer overflow interrupt mask 0: mask interrupt 1: mask none 0 m_rx_under r/w 1 reception buffer underflow interrupt mask 0: mask interrupt 1: mask none downloaded from: http:///
147/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 ic_raw_intr_stat generated interrupt address offset : 0x34 bits name r/w default mo de description 31:12 reserved n/a - - - 11 gen_call r 0 s general call demand interrupt 0: no response 1: general call request response 10 start_det r 0 m/s beginning of transmission interrupt 0: start condition not detected 1: start condition detected 9 stop_det r 0 m/s end of transmission interrupt 0: stop condition not detected 1: stop condition detected 8 activity r 0 m/s interrupt during transmission this register is set during i2c transmission. value remains until it is possible to clear from the idle state. reset condition: ? i2c error. ? ic_clr_activity register read ? ic_clr_intr register read ? system reset 0: no transmission 1: initial transmission during i2c activity 7 rx_done r 0 s reception complete interrupt when there is nack from the i2c master during transmission, this bit is set. 0: incomplete reception 1: complete reception 6 tx_abrt r 0 m/s transmission abort interrupt the transmission abort occurs when there is nack after first byte is transmitted (i2c master mode). refer to ic_tx_abrt_source for the set condition. 0: no abort 1: transmission abort 5 rd_req r 0 s reception request interrupt this register is set when there is reception request (read) from other i2c masters in i2c slave mode. (the i2c bus maintains its value until it is changed to waiting state ) 0: no request 1: read request ic_raw_intr_stat C continued bits name r/w default mode description 4 tx_empty r 0 m/s empty transmission buffer interrupt 0: transmission buffer level > ic_tx_tl 1: transmission buffer level ic_tx_tl 3 tx_over r 0 m/s transmission buffer overflow interrupt 0: no overflow on transmission buffer 1: transmission buffer overflow 2 rx_full r 0 m/s reception buffer full interrupt 0: reception buffer level ic_rx_tx 1: reception buffer level > ic_rx_tl 1 rx_over r 0 m/s reception buffer overflow interrupt 0: no overflow on reception buffer 1: reception buffer overflow 0 rx_under r 0 m/s set when there are reception buffer level =0 ic_data_cmd register reading downloaded from: http:///
148/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 ic_rx_tl memory threshold setting for receive fifo address offset : 0x38 bits name r/w default description 31:8 reserved n/a - - 7:0 rx_tl r 0x00 threshold for rx_full interrupt ic_tx_tl memory threshold setting for transmit fifo address offset : 0x3c bits name r/w default description 31:8 reserved n/a 7:0 tx_tl r 0x00 threshold for tx_empty interrupt ic_clr_intr this register clears all interrupts. address offset : 0x40 bits name r/w default description 31:1 reserved n/a - - 0 clr_intr r 0 all the interrupt clears after reading. ic_clr_rx_under set this register when ic_data_cmd is read to empty receive fifo and clears interrupt. address offset : 0x44 bits name r/w default description 31:1 reserved n/a - - 0 clr_rx_under r 0 the rx_under interrupt clears after reading. ic_clr_rx_over this register clears the interrupt generated when data is done fr om the i2c interface to full receptionfifo in reception. address offset : 0x48 bits name r/w default description 31:1 reserved n/a - - 0 clr_rx_over r 0 the rx_over interrupt is cleared after reading. ic_clr_tx_over this register clears the interrupt set when ic_data_cmd is written in full transmissionfifo. address offset : 0x4c bits name r/w default description 31:1 reserved n/a - - 0 clr_tx_over r 0 the tx_over interrupt is cleared after reading. ic_clr_rd_req this register clears the interrupt when there is rec eption request from other i2c masters (in slave mode). address offset : 0x50 bits name r/w default description 31:1 reserved n/a - - 0 clr_rd_req r 0 the rd_req interrupt is cleared after reading. ic_clr_tx_abrt this register clears the interrupt generated when transmission is aborted. address offset : 0x54 bits name r/w default description 31:1 reserved n/a - - 0 clr_tx_abrt r 0 ic_tx_abrt_source register clears the interrupt by reading tx_abrt. ic_clr_rx_done this register clears the interrupt when reception resp onse is completed during transmission as i2c slave. address offset : 0x58 bits name r/w default description 31:1 reserved n/a - - 0 clr_rx_done r 0 the rx_done interrupt is cleared. downloaded from: http:///
149/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 ic_clr_activity this register clears the interrupt during the start of i2c interface transmission. address offset : 0x5c bits name r/w default description 31:1 reserved n/a - - 0 clr_activity r 0 the activity interrupt is cleared. ic_clr_stop_det this register clears the interrupt set at the stop condition in the i2c interface. address offset : 0x60 bits name r/w default description 31:1 reserved n/a - - 0 clr_stop_det r 0 the stop_det interrupt is cleared after reading. ic_clr_start_det this register clears the interrupt set at the start condition in the i2c interface. address offset :1 0x64 bits name r/w default description 31:1 reserved n/a - - 0 clr_start_det r 0 the start_det interrupt is cleared after reading. ic_clr_gen_call this register clears the interrupt set by the general call. address offset : 0x68 bits name r/w default description 31:1 reserved n/a - - 0 clr_gen_call r 0 the gen_call interrupt is cleared after reading. ic_enable this register enables i2c interface. please dis able after transfger in the i2c interface ends. address offset : 0x6c bits name r/w default description 31:1 reserved n/a 0 enable r/w 0 0: i2c is disabled. 1: i2c is enabled. ic_status the current state of i2c transmission and the state of fifo. address offset : 0x70 bits name r/w default description 31:5 reserved n/a - - 4 rff r 0 0: receive fifo is not full. 1: receive fifo is full. 3 rfne r 0 0: receive fifo is full. 1: receive fifo has data. 2 tfe r 1 0: transmit fifo is not empty. 1: transmit fifo is full. 1 tfnf r 1 0: transmit fifo is full. 1: transmit fifo is not full. 0 activity r 0 0: idle 1: i2c is in transmission state ic_txflr the current state of the fifo memory for transmission. address offset : 0x74 bits name r/w default description 31:7 reserved n/a - - 5:0 txflr r 0x0 transmission buffer level (0 to 32) ic_rxflr the current state of the fifo memory for reading. address offset : 0x78 bits name r/w default description 31:4 reserved n/a - - 5:0 rxflr r 0x0 reception buffer level(0 to 32) downloaded from: http:///
150/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 ic_sda_hold length setting of sda hold time register. the unit is ic_clk. address offset : 0x7c bits name r/w default description 31:16 reserved n/a - - 15:0 ic_sda_hold r/w 0x01 sda hold time setting ic_tx_abrt_source the i2c transmission abort register address offset : 0x80 bits name r/w default mode description 31:16 reserved n/a - - - 15 abrt_slvrd_intx r 0 s if cmd=1 after the reception request is received from the master, this bit is set. 0: no abort 1: abort 14 abrt_slv_arblost r 0 s when arbitration doesnt permit communication, this bit is set (bit 12 is set at the same time). 0: no abort 1: abort 13 abrt_slvflush_txfifo r 0 s the buffer is cleared when there is data in the transmission buffer when the reception request is received. then this bit is set.0: no abort 1: abort 12 abrt_lost r 0 m/s when arbitration doesnt permit communication from master devices or when bit 14 is set, this bit is also set. 0: no abort 1: abort 11 abrt_master_dis r 0 when the function that disables the master is set, this bit is also set 0: no abort 1: abort 10 abrt_10b_rd_norstrt r 0 m in 10-bit address mode, when the read command is sent and the restart function is in disabled state (ic_restart_en=0), this bit is set. 0: no abort 1: abort 9 abrt_sbyte_norstrt r 0 m when the start byte is sent during transmission using the ic_tar register and the restart function is in disabled state, this bit is set. transmission using the i2c bus is not done at this time. 0: no abort 1: abort 8 abrt_hs_norstrt r 0 0 always 7 abrt_sbyte_ackdet r 0 m this bit is set when there ack response during transmission of start byte (abnormal operation). 0: no abort 1: abort 6 abrt_hs_ackdet r 0 fixed to low downloaded from: http:///
151/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 ic_tx_abrt_source C continued bits name r/w default mode description 5 abrt_gcall_read r 0 m when the reading command is sent when the general call is sent, it is set. 0: no abort 1: abort 4 abrt_gcall_noack r 0 m it is set when there is no ack response to the general call. 0: no abort 1: abort 3 abrt_txdata_noack r 0 m it is set when there is no ack response for data transmission. 0: no abort 1: abort 2 abrt_10addr2_noack r 0 m it is set when there is no ack response to transmission of ten bit address mode in the second the byte in address. 0: no abort 1: abort 1 abrt_10addr1_noack r 0 m it is set when there is no ack response to transmission of ten bit address mode in the first the byte in address. 0: no abort 1: abort 0 abrt_7b_addr_noack r 0 m it is set when there is no ack response to address transmission of seven bit address mode. 0: no abort 1: abort dmacr the dma control register address offset : 0x88 dmatdlr the dma transmission data level address offset : 0x8c ic_dma_rdlr the fifo threshold register for reception address offset : 0x90 bits name direction reset description 31:5 reserved n/a - - 4:0 dmardlr r/w 0x0 reception data level timing in which the dma request is done. dma_rx_req signal is outputted when the data (value + 1) collected in fifo becomes equal and rdame=1. bits name direction reset description 1 tdmae r/w 0x0 transmit dma is enable. the dma channel is turned on and off with this bit. 0: transfer dma is disable 1: transfer dma is enable 0 rdmae r/w 0x0 receive dma is enable. the dma channel is turned on and off with this bit. 0: reception dma is disable 1: reception dma is enable bits name direction reset description 4:0 dmatdlr r/w 0x0 transmission data level timing in which the dma request is done. when equal, tdame=1, dma_tx_req signal is outputted based on the number of data collected in fifo as the set value. downloaded from: http:///
152/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 ic_sda_setup (possible to modify only if ic_enable 0=0) sda setup timing register setting (the unit is ic_clk) address offset : 0x94 bits name direction reset description 31:8 reserved n/a - - 7:0 sda_setup r/w 0x64 this register sets sda setup timing. minimum value is two. ic_ack_general_call the general call response (ack) setting register address offset : 0x98 bits name direction reset description 31:1 reserved n/a - - 0 ack_gen_call r/w 0x1 when general call is done during reception, the ack response is generated. ic_enable_status when ic_enable 0 is set from 1 to 0, the hardware status of i2c can be read. address offset : 0x9c bits name direction reset description 31:3 reserved n/a - - 2 slv_rx_data_l ost r 0x0 when i2c slave mode reception is disabled, data byte reception status can be read. 0: data is not reception when disabled. 1: data is reception when disabled. 1 slv_disabled_ whhile_busy r 0x0 the address byte and the data byte are set for i2c to be disabled during reception by the i2c slave mode. 0 ic_en r 0x0 0: i2c is disabled. 1: i2c is active. ic_fs_spklen the spike control limit value setting register of the fast mode or standard mode (the unit is ic_clk) address offset : 0xa0 bits name direction reset description 31:8 reserved n/a - - 7:0 ic_fs_spklen r/w 0x1 the width of the filtered glitch: minimum value is one. downloaded from: http:///
153/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 14. uart0/uart1 14.1. feature ? it is connected with the apb interface of the amba standard. ? its system clock of dw_apb_uart is independent to the apb interface clock. ? the width of the apb bus is 32 bits. ? its function is based on is16550. ? the width of transmitted and received data is fixed to 8 bits. ? the width of fifo data is fixed to 8 bits. ? the depth of transfer source fifo is 32 bits, ? fifo can be selected, enabled and disabled. ? it has auto-flow control mode similar to standard is16750 (only in uart0). ? it has the transmitter holding register empty (thre) interrupt mode. ? the baud rate can be calculated by: ? it uses 96 mhz serial clock. ? it uses handshake for transmission and reception in the dma interface. 14.2. description 14.2.1. uart serial protocol the serial data in one transaction of the dw_apb_ uart circuit format is shown in figure 59. figure 59. serial data format after the start bit, the data bit is sent from lsb. the parity bit that does the error check of the received data is added befo re the stop bit after msb of data. moreover, the parity bit is an option. stop bits are 1, 1.5 or 2 bits, and it continues after t he parity bit. the width of the sending and receiving data or parity, etc. can be set by the lcr register. as for all transmission bits, transmission is done accurately at same intervals of time. this is called bit period or bit time. 1 bit time is equal to 16 baud clock. the sample point of serial data reception is shown in figure 60. uart serial protocol C continued figure 60. sample point of received serial data divisor 16 frequence clock serial rate baud ? ? downloaded from: http:///
154/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 the received data is 16 cycles from the midpoint of the start bit after baud clock. out can do baud clock by the option. the timing diagram of baud clock is shown in figure 61. in dw_apb_uart, baud clock is controlled by sclk or pclk and divisor latch register(=divisor). moreover, the frequency of baud clock can be shown by the following expressions: figure 61. timing diagram of baud clock 14.2.2. buffer for transmission and reception dw_apb_uart can have fifo. the data width is fixed to 8 bits. t he fifo depth is 32. fifo is composed of d-ff. moreover, reading and writing for transmission and receive fifo are possible. this fifo function can be enabled or disabled according to the register. 14.2.3. interrupt interrupt can be done to any of the five fixed priority levels attached to dw_apb_uart.. moreover, inte rrupt can be enabled or disabled in the ier register. examples of interrupt occurrenc e are shown as follows. please refer to the iir register for details. ? when reception error occurs ? when the reception data can be used ? when fifo is used, character time-out is generated ? when fifo for transmission becomes below the threshold when the thre interrupt is used ? modem status dw_apb_uart has thre interrupt (transmitter holding regist er empty interrupt). when the transmission data becomes below a set threshold of transmissionfifo, interrupt is generated. divisor 16 frequence clock serial rate baud ? ? downloaded from: http:///
155/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 14.2.4. auto-flow control (uart0 only) dw_apb_uart has auto-flow control mode compatible with is16750. signals rts_n and cts_n are active low. the terminal rts_n should be connected with the terminal cts_n of other ua rt when using auto-flow control. when the received data exceeds the threshold of fifo, rts_n goes low. however, when auto-flow control is used, irda 1.0 sir cannot be supported. the timing diagram of auto rts and auto cts is shown in figure 62 and figure 63. figure 62. timing diagram of auto rts rts_n becomes high when the received data exceeded the threshold of fifo in figure 62 rts_n becomes low when device has finished reading the data that exists in receive fifo. figure 63. timing diagram of auto cts when cts_n becomes high infigure 63 transmission of data is temporarily interrupted. when cts_n becomes low, transmission of data is exeucted again. downloaded from: http:///
156/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 14.3. i/o signal uart prdata dtr_n rts_n out2_n out1_n dma_tx_req dma_rx_req dma_tx_single dma_rx_single sout baudout_n intr sin pclk presetn penable pwrite pwdata paddr psel sclk s_rst_n scan_mode cts_n dsr_n dcd_n ri_n dma_tx_ack dma_rx_ack figure 64. uart module downloaded from: http:///
157/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 terminal list of dw_apb_uart terminal name i/o description connection pclk in apb clock clock gen presetn in apb reset reset gen psel in apb peripheral select signal apb paddr in apb sddress [7:0] apb pwdata in apb write data [31:0] apb pwrite in apb write signal apb penable in apb enable signal apb prdata out apb read data [31:0] apb sclk in serial clock clock gen s_rst_n in serial reset signal reset gen scan_mode in scan mode select signal testdec cts_n in transmission clear signal i/o dsr_n in data set signal "hi fixation" dcd_n in data carry detection signal "hi fixation" ri_n in ring indicator signal "hi fixation" dma_tx_ack in dma transmission acknowledge dmac dma_rx_ack in dma reception acknowledge dmac dtr_n out data terminal signal open rts_n out transmission request signal i/o out2_n out programmable signal 2 open out1_n out programmable signal 1 open dma_tx_req out dma transmission request dmac dma_tx_single out dma transmission request dmac dma_rx_req out dma reception request dmac dma_rx_single out dma reception request dmac sin in serial in i/o sout out serial out i/o intr out interrupt signal ictl baudout_n out baud clock out signal open downloaded from: http:///
158/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 14.4. register 14.4.1. memory map name description address offset r/w width reset rbr receive buffer register lcr 7 = at 0 0x00 r 8 bit 0x0 thr transmit holding register lcr 7 = at 0 w 8 bit 0x0 dll divisor latch (low) lcr 7 = at one r/w 8 bit 0x0 dlh divisor latch (high) lcr[7] = at 1 0x04 r/w 8 bit 0x4 ier interrupt enable register lcr[7] =at 0 r/w 8 bit 0x0 iir interrupt identification register 0x08 r 8 bit 0x1 fcr fifo control register w 8 bit 0x0 lcr line control register 0x0c r/w 8 bit 0x0 mcr modem control register 0x10 r/w 8 bit 0x0 lsr line status register 0x14 r 8 bit 0x60 msr modem status register 0x18 r 8 bit 0x0 scr scartchpad register 0x1c r/w 8 bit 0x0 reserved - 0x20 C 0x2c - - - far fifo access register 0x70 r/w 1 bit 0x0 usr uart status register 0x7c r 5 bit 0x6 tfl transmit fifo level 0x80 r 6 bit 0x0 rfl receive fifo level 0x84 r 6 bit 0x0 htx halt tx 0xa4 r/w 1 bit 0x0 dmasa dma software acknowledge 0xa8 w 1 bit 0x0 reserved - 0xac C 0xf0 - - - ucv uart component version 0xf8 r 32 bit 0x3331 342a ctr component type register 0xfc r 32 bit 0x4457 0110 downloaded from: http:///
159/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 14.4.2. register detail rbr (receive buffer register) address offset : 0x0 thr (transmit holding register) address offset : 0x0 dlh (divisor latch high) address offset : 0x4 dll (divisor latch low) address offset : 0x0 bits name direction reset description 7:0 receive buffer register r 0x0 reception buffer register for serial in lsr 0 = at one, the read data is valid. fcr 0 = it can access the head of fifo at one (selected fifo). bits name direction reset description 7:0 transmit holding register w 0x0 transmission data register for serial out thre = write data none at one (lsr 5). fcr 0 = 1(selected fifo) and thre = the size of fifo that can be written at one. bits name direction reset description 7:0 divisor latch (high) r/w 0x0 the higher bits of divisor latch register (dlr) which sets the value of baud rate.this register becomes accessible when dlab bit (lcr 7) is set to "1", and when usr 0 bit is "0". the baud rate can be calculated using the following expressions: baud rate = (serial clock freq) / (16 * dlr) it is necessary to send and receive dataq after 8 clock cycles even if dlr was set to the slowest clock conversion in dw_apb_uart. bits name direction reset description 7:0 divisor latch (low) r/w 0x0 the lower bits of divisor latch register (dlr), to be formed with dlh register. this register becomes accessible when dlab bit (lcr 7) is set to "1", and when usr 0 bit is "0". the baud rate can be calculated using the following expressions: baud rate = (serial clock freq) / (16 * dlr) it is necessary to send and receive dataq after 8 clock cycles even if dlr was set to the slowest clock conversion in dw_apb_uart.. downloaded from: http:///
160/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 ier (interrupt enable register) address offset : 0x4 iir (interrupt identify register) address offset : 0x8 (note 1) details of interrupt id bits name direction reset description 7 ptime r/w 0x0 thre interrupt enable signal 0 = disabled 1 = enabled 6:4 reserve and read as zero 3 edssi r/w 0x0 modem status interrupt enable signal this interrupt has a high priority level of 4. 0 = disabled 1 = enabled 2 elsi r/w 0x0 reception line status interrupt enable signal this interrupt has the highest priority level. 0 = disabled 1 = enabled 1 etbei r/w 0x0 tranmission maintenance register empty (thre) interrupt enable signal this interrupt has a high priority level of 3. 0 = disabled 1 = enabled 0 erbfi r/w 0x0 reception data and character timeout interrupt enable signal (fifo is effective) this interrupt has a high priority level of 2. 0 = disabled 1 = enabled bits name direction reset description 7:6 fifos enabled r 0x0 fifo enable signal 00 = disabled 11 = enabled 5:4 reserve and read as zero 3:0 interrupt id (note 1) r 0x1 interrupt id 0000 = modem status 0001 = no pending interrupt 0010 = thr empty 0100 = received data available 0110 = reception line status 0111 = busy detect 1100 = character timeout downloaded from: http:///
161/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 iir (interrupt identify register) C continued fcr (fifo control register) address offset : 0x8 id priority meaning interrupt generation factor interrupt reset 0001 none none 0110 1 ( the height ) reception line status overrun / parity / framing error / break generation line status register (lsr) was read. 0100 2 reception data effective when fifo is invalid, the reception data became effective. when fifo is valid, tt reached at the fifo trigger level. when fifo is invalid fifo that read reception buffer register (rbr) became below the fifo trigger level when it was valid. 1100 2 character time-out interrupt is generated when more than one character data remained in fifo and device did not accessed it in the fixed amount of time (four character time). reception buffer register (rbr) was read. 0010 3 thr is empty. the thre mode where thr is empty and fell below the fifo threshold when it was valid. or that read iir it wrote it in thr (fifo or thre was invalid) or transmit fifo became more than the threshold. (thre is effective. ) 0000 4 modem status clear to send (cts) / data set ready (dsr) / ring indicator (ri) / data carrier detect (dcd) generation modem status register (msr) was read. 0111 5 busy detection interrupt is generated when device writes to line control register (lcr) while uart is busy. uart status register (usr) was read. bits name direction reset description 7:6 rcvr trigger w 0x0 the threshold of receive fifo is selected. 1. interrupt generation 2. it is used to de-assert rts_n signal at auto_flow_control upon receipt of data. 3. it is used for dma_rx_req_n signal assert of the dma handshake. 00 = there is one character. 01 = fifo 1/4 10 = fifo 1/2 11 = there are two characters in fifo. 5:4 tx empty trigger w 0x0 the threshold of transmit fifo is selected. 1. thre interrupt generation 2. it is used for assert of the dma_tx_req_n signal of the dma handshake. 00 = the fifo is empty. 01 = there are two characters in fifo 10 = fifo 1/4 11 = fifo 1/2 3 - w 0x0 this bit is only valid when dma handshake interface is not used. 2 xmit fifo reset w 0x0 transmit fifo clear bit transmission request via dma handshake is cleared. this bit is cleared automatically. 1 rcvr fifo reset w 0x0 receive fifo clear bit reception request via dma handshake is cleared. this bit is cleared automatically. 0 fifo enable w 0x0 transmission and receive fifo enable signal downloaded from: http:///
162/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 lcr (line control register) address offset : 0xc mcr (modem control register) address offset : 0x10 bits name direction reset description 7 dlab r/w 0x0 dll and dlh write enable for baud rate setting writing to this bit is only possible when usr 0 = 0. please clear this bit after setting the baud rate. 6 break r/w 0x0 it enters in the state of the transmission hit. 5 stick parity reserve and read as zero 4 eps r/w 0x0 parity select signal (parity is enabled) writing to this bit is only possible when usr 0 = 0. 0: odd parity 1: even parity 3 pen r/w 0x0 parity enable signal writing to this bit is only possible when usr 0 = 0. 0 = parity is disabled. 1 = parity is enabled. 2 stop r/w 0x0 it is used to select the number of stop bits of each character. writing to this bit is only possible when usr 0 = 0. 0 = 1 stop bit 1 = 1.5 stop bit at time lcr [1:0] = 0 1 = 2 stop bit at other time 1:0 dls r/w 0x0 data length select writing to this bit is only possible when usr 0 = 0. it is used to select the number of data bits in one character. 00=5 bits 01=6 bits 10=7 bits 11=8 bits bits name direction reset description 6 sire r 0x0 sir mode enable signal writing to this bit is not possible because irda mode is not supported. 5 afce r/w 0x0 auto-flow control enable signal when this bit is set to 1, the selected fifo operates in auto-flow control mode. 0 = auto-flow control mode is disabled 1 = auto-flow control mode is enabled. 4 loop back r/w 0x0 loop back test mode 0 = normal mode 1 = loop back mode in loop back mode, terminal sout is fixed to high and serial out is connected to an internal sin line. 3 out2 r/w 0x0 it is used to control out2_nout of the user definition directly. 0 = out2_n de-asserted (= 1) 1 = out2_n asserted (= 0) 2 out1 r/w 0x0 it is used to control out1_nout of the user definition directly. 0 = out1_n de-asserted (= 1) 1 = out1_n asserted (= 0) 1 rts r/w 0x0 it is used to control transmission request (rts_n) out directly. 0 = rts_n de-asserted (= 1) 1 = rts_n asserted (= 0) this bit is asserted when device is in auto-flow control mode and when receive fifo is below threshold. 0 dtr r/w 0x0 data terminal ready it is used to control data terminal preparation completion (dtr_n) out directly. 0 = dtr_n de-asserted (= 1) 1 = dtr_n asserted (= 0) downloaded from: http:///
163/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 lsr (line status register) address offset : 0x14 bits name direction reset description 7 rfe r 0x0 receiver fifo error bit this bit asserts when a parity or framing error in receive fifo occurs. 0 = no error in rx_fifo 1 = error in rx_fifo when the character with the error is at the head of receive fifo, and the lsr register is read when there is no error, this bit is cleared. 6 temt r 0x1 transmitter empty bit this bit asserts when transmission shift register and transmit fifo (when valid) are both empty. fifo sets the transmission register and the transmission shift register when it is invalid and sets this bit when both registers are empty. 5 thre r 0x1 transmit holding register empty bit this bit is asserted when the thre mode is invalid, and when the transmission register or transmit fifo is empty. this bit is set to 1 when data transfer is executed but there are data available for transmission from the transmission register or transmit fifo to transmission shift register. in this case, interrupt is generated. the thre mode and fifo show whether transmit fifo is full or not when it is effective. at this time, the thre interrupt is controlled by fcr [5:4]. 4 bi r 0x0 break interrupt bit it is used to show the detection of the break sequence on serial in data. this bit is cleared once it is read. 3 fe r 0x0 framing error bit it is used to detect framing error in the receive fifo. it happens when an effective stop bit in the reception data cannot be detected. this bit is cleared once it is read. 0 = no framing error 1 = framing error 2 pe r 0x0 parity error bit it is used to detect parity error in the receive fifo. this bit is cleared once it is read. 0 = no parity error 1 = parity error 1 oe r 0x0 overrun error bit it is used to detect if overrun error occurred. overrun occurs when new data is generated before old data is read. 0 = no overrun error 1 = overrun error 0 dr r 0x0 data ready bit it is asserted when there is at least one character in rbr or receive fifo. 0 = no data ready 1 = data ready downloaded from: http:///
164/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 msr (modem status register) address offset : 0x18 scr (scratchpad register) address offset : 0x1c bits name direction reset description 7 dcd r 0x0 data carrier detect this is used to show current status of modem control line dcn_n. 0 = dcd_n input de-asserted (= 1) 1 = dcd_n input asserted (= 0) it is the same as mcr [3] at the loop back mode. 6 ri r 0x0 ring indicator this is used to show current status of modem control line ri_n. 0 = ri_n input de-asserted (= 1) 1 = ri_n input asserted (= 0) it is the same as mcr [2] at the loop back mode. 5 dsr r 0x0 data set ready this is used to show current status of modem control line dsr_n. 0 = dsr_n input de-asserted (= 1) 1 = dsr_n input asserted (= 0) it is the same as mcr [0] at the loop back mode. 4 cts r 0x0 this is used to show current status of modem control line cts_n. 0 = cts_n input de-asserted (= 1) 1 = cts_n input asserted (= 0) it is the same as mcr [1] at the loop back mode. 3 ddcd r 0x0 delta data carrier detect this is used so that msr may show that modem control line dcd_n changed after reading of msr. 0 = no change on dcd_n since last read of msr 1 = there is a change on dcd_n since last read of msr this bit is cleared by reading. changing of mcr [3] is at the loop back mode. 2 teri r 0x0 trailing edge ring indicator this is used so that msr may show that ri_nln changed after reading of msr. 0 = no change on ri_n since last read of msr 1 = there is a change on ri_n since last read of msr this bit is cleared by reading. changing of mcr [2] (h -> l) is shown at the loop back mode. 1 ddsr r 0x0 delta data set ready this is used so that msr may show that modem control line dsr_n changed after reading of msr. 0 = no change on dsr_n since last read of msr 1 = there is a change on dsr_n since last read of msr this bit is cleared by reading. changing of mcr [0] is shown at the loop back mode. 0 dcts r 0x0 delta clear to send this is used so that msr may show that modem control line cts_n changed after reading of msr. 0 = no change on cts_n since last read of msr 1 = there is a change on cts_n since last read of msr this bit is cleared by reading. changing of mcr [1] is shown at the loop back mode. bits name direction reset description 7:0 scratchpad register r/w 0x0 the programmer uses this register as temporary storage space. it doesn't have any defined purpose in dw_apb_uart. downloaded from: http:///
165/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 far (fifo access register) address offset : 0x70 usr (uart status register) address offset : 0x7c tfl (transmit fifo level) address offset : 0x80 rfl (receive fifo level) address offset : 0x84 htx (halt tx) address offset : 0xa4 dmasa (dma software acknowledge) address offset : 0xa8 bits name direction reset description 0 fifo access register r/w 0x0 it is used to enable the fifo access mode for test. when this bit is set to 1, it is possible to read and write to transmission and receive fifo. 0 = disabled 1 = enabled bits name direction reset description 4 rff r 0x0 receive fifo full this is used to show that receive fifo is full. 0 = receive fifo is not full. 1 = receive fifo is full. 3 rfne r 0x0 receive fifo not empty this is used to show that there is one or more data in receive fifo. 0 = receive fifo is empty. 1 = receive fifo is not empty. 2 tfe r 0x1 transmit fifo empty this is used to show that transmit fifo is empty. 0 = transmit fifo not empty. 1 = transmit fifo is empty. 1 tfnf r 0x1 transmit fifo not full this is used to show that transmit fifo is not full. 0 = transmit fifo is full 1 = transmit fifo is not full 0 busy r 0x0 uart busy it is used to show that the serial transfer is in progress. 0 = dw_apb_uart is idle or inactive 1 = dw_apb_uart is busy bits name direction reset description 5:0 transmit fifo level r 0x0 transmit fifo level this shows the number of data in transmit fifo. bits name direction reset description 5:0 recieve fifo level r 0x0 receive fifo level this shows the number of data in receive fifo. bits name direction reset description 0 halt tx r/w 0x0 this register is used to stop transmission for test. 0 = halt tx disabled 1 = halt tx enabled bits name direction reset description 0 dma software acknowledge w 0x0 dma software acknowledge. this bit is asserted when dma request is done without error. this bit is cleared automatically. downloaded from: http:///
166/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 ucv (uart component version) address offset : 0xf8 ctr (component type register) address offset : 0xfc bits name direction reset description 31:0 uart component version r 0x333 0312 a ascii value of component version bits name direction reset description 31:0 peripheral id r 0x445 70110 peripheral id downloaded from: http:///
167/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 15. i2s input i/f and cd-rom decoder 15.1. features 2-ch digital audio input x 2 i2s/eiaj format 16-bit data selectable bit clock from 32 fs, 48 fs, and 64 fs selectable input sample rate from 32 khz, 44.1 khz, and 48 khz one line of internal input from the cd servo controller up to 4 ? maximum input rate supports cd-da link detection supports cd-rom sync detection supports cd-rom data descrambling acquires sub-q data acquires cd-text data built-in dma 15.2. description 15.2.1. block diagram the following figure shows an i2s input controller block diagram. figure 65. i2s input controller block diagram downloaded from: http:///
168/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 15.2.2. serial-to-parallel conversion thr ough 3-wire (3-line) input interface the i2s input interface converts serial data input through a 3-wire interface from cd-da and cd-rom to parallel data. the interface supports 16- and 24-bit input data width. to in put 24 bits of data, the bottom 8 bits of data are dropped. this allows input of signals in a variety of formats by setting clock-edge polarity, etc. the interface has a total of three input lines - two lines fr om pad and one line from the internal cd-dsp. these lines are designed for exclusive use. 15.2.3. inreqi for input of 1 sample data (lr ? 32), the data is considered valid when inreqi is set to h at the end of sample data input. when inreqi is set to l, the data is considered invalid and is not written to the internal buffer. 15.2.4. bfullo bfullo becomes h when writing to buffer cannot be executed. (when ready bit of selected fifo is l). bfullo becomes l when inreqi is l and sample input data has is written successfully to buffer (when ready bit of selected fifo is h). figure 66 15.2.5. receive buffer the receive buffer uses part of working ram as receiv e fifos and has 8-byte fifos as registers in the circuit. the receive buffer can configure four fifo areas with buffer size up to 4,095 bytes. fifos are written in the order of no. 1, 2, 3, 4, 1, 2, ? when written data reaches the set fifo size, a termination interrupt is generated to write data to the subsequent fifo. at this time, unless ready of the subsequent fifo is set to h, the receive buffer is considered full so data write is not possible. to avoid this event, set ready of the subsequent or later fifos to h before the completion of the previous fifo. dma is automatically conducted from the set fifo start address until the set number of transfers is completed. working ram addresses are automatically incremented from the start address. in order to prevent failures to acquire data for interpolation, configure the four fifo areas as shown below for receiving data from cd-rom. stack sync fifo in 12 bytes in each area. start address size rx fifo1: addr1 2364byte rx fifo2: addr1 + 2352 byte 2364byte rx fifo3: addr2 + 2352 byte 2364byte rx fifo4: addr3 + 2352 byte 2364byte downloaded from: http:///
169/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 15.2.6. cd-rom input when the cd-rom input function is enabl ed, it detects a synchronous patt ern (96h00ff_ffff_ff ff_ffff_ffff_ff00) in the sector for an input signal. data are written in the internal buffer from the data after the synchronous pattern is detected (i.e., from the 13th byte). synchronous sector detection state includes three states: open, state0, and state1. open state is a state in which no synchronous pattern has been det ected. in this state, the internal counter is not working and, as a result, no data are written to the internal ram. w hen a synchronous pattern is detected, the detection state is switched to state0. in state0, every time a synchronous sector pattern is inputted, it is detected as the synchronous pattern. when a subsequent synchronous pattern is detected in a sector containing 2,352 bytes in state0, the detection state is switched to state1. if no synchronous pattern is inputted in a sector containing 2,352 or more bytes in state0, the synchronous pattern is considered lost and t he detection state is switched to open state. in state1, the detection of patterns in a sector within ? 16 bytes from the position in which normal synchronous pattern was detected is regarded as the detection of synchronous pattern, and detection in any positions other than the said position is ignored. the detection of synchronous pattern in a sector within ? 12 bytes from the position in which normal synchronous pattern was detected is regarded as the detection of synchronous pattern from back gate. if no synchronous pattern is inputted in a sector within ? 16 or ? 12 bytes from the position in which normal synchronous pattern was detected in state1, the synchronous pattern is considered lost to interpolate and wr ite data to the counter or ram. if no synchronous pattern is detected in a sector containing 2,352 bytes in state1, the detection state is switched to state0. 12 to 2,351 bytes of data in each sector are descrambled by the feedback shift register corresponding to x15+x+1. (0 to 11 bytes in a sector are used for synchronous patterns.) when a sector status in each stage of dma fifo is defined, an interrupt is generated. sector status are read from the register. downloaded from: http:///
170/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 figure 67. {? ??r?_rz?k I ?? _ _ _ _ __ _ _ _ _ __ _ _ _ _ _ ? __ _ _ __ _ ? _ cd-rom data storage format fifo size: 2,352 bytes ? 12 bytes ? 2,364 bytes/area note: an interrupt is generated when data acquisition is completed and sector status is defined in each area. note: overwrite data in the sync area b y fw. overwrite interpolation downloaded from: http:///
171/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 15.2.7. error correction ecc after completion of setting the sector start address (i.e., 0th byte in the synchronous area) to the dma start address setting register for ecc and edc, ecc is started by having a write a ccess to the ecc start register. ecc makes pq corrections to the cd-rom mode1 format for the set number of correction times regardless of mode and form settings. when ecc is completed, a termination interrupt is generated. the correct ion results can be read from the status register moni4. determine the presence or absence of uncorrectable data after completion of corrections for the set number of times using pqucf_flag bit 8. for mode2 form1, fill data with zeros in the header area, and then execute ecc. edc after completion of start address setting, edc is exec uted to any of cd-rom mode 1, mode2 form1, and mode2 form2 formats according to edcmode register setting by having write access to the edc start register. when edc is completed, a termination interrupt is generated. the correction results can be read from the status register. for mode1, fill data with zeros in the sync area, and then execute edc. required cycle number (calculated with 96 mhz operating frequency) input data: wav data (48 khz stereo sampling frequency) format: mode1or mode2 form1 2,048 bytes for user data per sector ? 512 bytes of sample data ? 1024,000 cycles ? 10.67 ms wait_busreq register setting: 14 (dec) (minimum hbusreq cycles: 32 per system clock) 1 ? pq correction ? 38,373 cycles 3 ? edc ? 27,128 cycles 1 ? pq correction ? 3 ? edc ? 65,500 cycles ? 1.36 ms ? 6.4% note: cycles including master with priority level higher th an cd-rom (i.e., usb, i2s out, sdio, and cdin) are additionally applied to bus arbitration. figure 68 ? ? ? ? ? ? ? ? ? ? ? ? heade r user data cd-rom format s y nc sync s y nc sync sync header header header header zero data user data use r data user data zero sub header sub header downloaded from: http:///
172/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 15.2.8. sub-q data and cd-text data acquisition retrieve sub-q data and cd-text data from subcode data of cd-dsp. generate 12-byte sub-q data [95:0] and 18-byte cd-text data [143:0]. when these data are completed, an interrupt is generated. retrieved data can be read from the register. careful attention should be paid to the byte order of sub-q [95:0] and cd-text [143:0]. normally, sub-q data are given small numbers to bytes received earlier such as q1, q2, ? giving numbers according to this rule comes from sub-q [95] ? q1, sub-q [94] ? q2, ?? , and sub-q [0] ? q96 the same rule applies to cd-text [143:0]. cd-text [143] represents a byte received first. downloaded from: http:///
173/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 15.3. i/o signals pin name i/o function destination sys_clk_i in apb bus clock clkctr cdin_clk__i in cd-in clock clkctr cdec_clk__i in cd-rom clock clkctr rstb_i in reset (active low) rstgen peri_addr_i in apb bus address apb peri_en_i in apb bus enable apb peri_di_i in apb bus write data apb peri_we_i in apb bus write enable apb psel_i in apb bus selector apb peri_do_o out apb bus read data apb hgrant_i in master x bus grant for audio data pdmac ahb hrespm_i[1:0] in ram transport response for audio data pdmac ahb hreadymi_i in ram transport finish for audio data pdmac ahb hrdatam_i in ram read data for audio data pdmac ahb hbusreq_o out master x bus request for audio data pdmac ahb htrans_o[1:0] out master x transport type for audio data pdmac ahb hsize_o[1:0] out master x transport size for audio data pdmac ahb hwrite_o out master x transport direction for audio data pdmac ahb haddr_o[19:0] out master x address for audio data pdmac ahb hwdata_o[31:0] out master x write data for audio data pdmac ahb hgrant_cdrom_i in master x bus grant for cd-rom ecc pdmac ahb hrespm_cdrom_i[1:0] in ram transport response for cd-rom ecc pdmac ahb hreadym_cdromi_i in ram transport finish for cd-rom ecc pdmac ahb hrdatam_cdrom_i in ram read data for cd-rom ecc pdmac ahb hbusreq_cdrom_o out master x bus request for cd-rom ecc pdmac ahb htrans_cdrom_o[1:0] out master x tr ansport type for cd-rom ecc pdmac ahb hsize_cdrom_o[1:0] out master x transport size for cd-rom ecc pdmac ahb hwrite_cdrom_o out master x transport direction for cd-rom ecc pdmac ahb haddr_cdrom_o[19:0] out master x address for cd-rom ecc pdmac ahb hwdata_cdrom_o[31:0] out master x write data for cd-rom ecc pdmac ahb lrck_ch1_i in lr clock input from channel 1 pad bck_ch1_i in bit clock input from channel 1 pad data_ch1_i in data input from channel 1 pad lrck_ch2_i in lr clock input from channel 2 pad bck_ch2_i in bit clock input from channel 2 pad data_ch2_i in data input from channel 2 pad lrck_cddsp_i in lr clock input from cd-dsp cd-dsp bck_cddsp_i in bit clock input from cd-dsp cd-dsp data_cddsp_i in data input from cd-dsp cd-dsp sbsy_i in subcode block signal cd-dsp sfsy_i in subcode frame signal cd-dsp sbclk_o out subcode shift clock signal cd-dsp subd_i in subcode data signal cd-dsp i2sin_irq_o out interrupt (active low) ictl downloaded from: http:///
174/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 15.4. register 15.4.1. memory map name description address offset r/w width bit reset cdin_set0 cd-in input format setting 0x00 r/w 8 0x00 cdin_set1 dma/cd-rom setting 0x04 r/w 5 0x00 cdin_set3 rx fifo ready setting 0x0c r/w 4 0x0 cdin_set4 rx fifo1 start address setting 0x10 r/w 32 0x0 cdin_set5 rx fifo1 size setting 0x14 r/w 12 0x400 cdin_set6 rx fifo2 start address setting 0x18 r/w 32 0x0 cdin_set7 rx fifo2 size setting 0x1c r/w 12 0x400 cdin_set8 rx fifo3 start address setting 0x20 r/w 32 0x0 cdin_set9 rx fifo3 size setting 0x24 r/w 12 0x400 cdin_set10 rx fifo4 start address setting 0x28 r/w 32 0x0 cdin_set11 rx fifo4 size setting 0x2c r/w 12 0x400 cdin_set12 connection setting 0x30 r/w 8 0x80 cdin_set13 connection data 0 setting 0x34 r/w 32 0x00 cdin_set14 connection data 1 setting 0x38 r/w 32 0x00 cdin_set15 connection data 2 setting 0x3c r/w 32 0x00 cdin_set16 ecc/edc setting 0x40 r/w 21 0x0e0000 cdin_set17 ecc/edcdma start address setting 0x44 r/w 32 0x0 eccstart ecc start 0x48 w D 0x0 edcstart edc start 0x4c w D 0x0 irq_set0 irq mask setting 0x60 r/w 16 0xffff irq_set1 irq clear setting 0x64 r/w 16 0x0000 irq_set2 irq monitor 0x68 r 16 0xffff moni1 moni1 0x80 r 32 0x280 moni2 moni2 0x84 r 32 0x0 moni3 moni3 0x88 r 32 0x3ff0080 moni3b moni3b sector status monitor 0x8c r 16 0x0 moni4 cd-rom ecc status register 0x90 r 28 0x0 moni5 cd-rom edc status register 0x94 r 6 0x0 inreq inreq setting register 0x98 r/w 1 0x0 subq1 subq data acquisition register 1 0x9c r 32 0x00000000 subq2 subq data acquisition register 2 0xa0 r 32 0x00000000 subq3 subq data acquisition register 3 0xa4 r 32 0x00000000 cd-text1 cd-text data acquisition re gister 1 0xa8 r 32 0x00000000 cd-text2 cd- text data acquisition register 2 0xac r 32 0x00000000 cd-text3 cd- text data acquisition register 3 0xb0 r 32 0x00000000 cd-text4 cd- text data acquisition register 4 0xb4 r 32 0x00000000 cd-text5 cd- text data acquisition register 5 0xb8 r 16 0x0000 chansel input channel setting register 0xbc r/w 2 0x0 downloaded from: http:///
175/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 15.4.2. register detail cdin_set0 cd-in input format setting offset : 0x00 , reset : 0x00 bits name direction reset description 7:6 r/w 0x0 - 5 r/w 0x0 i2s mode setting 0: eiaj 1: i2s 4 r/w 0x0 lrck polarity setting 0: l-ch set to h 1: l-ch set to l 3 r/w 0x0 data width setting 0: 16 bits 1: 24 bits 2 r/w 0x0 data align setting 0: right-aligned 1: left-aligned 1 r/w 0x0 data lsb fast setting 0: msb fast 1: lsb fast 0 r/w 0x0 data latch setting 0: bck rising edge 1: bck falling edge cdin_set1 dma enable setting offset : 0x04 , reset : 0x00 bits name direction reset description 4 r/w 0x0 cd in dma enable setting 0: off 1: on 3 r/w 0x0 - 2 r/w 0x0 cd-rom sequence clear setting 0: not clear 1: clear 1 r/w 0x0 cd-rom descramble setting 0: descramble on 1: descrambleoff 0 r/w 0x0 cd-rom enable setting 0: off 1: on downloaded from: http:///
176/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 cdin_set3 rx fifo ready setting offset: 0x0c , reset : 0x00 bits name direction reset description 3 r/w 0x0 rx fifo4 ready write 1 to this register when data write is ready. the register is set to 0 upon completion of writing to the fifo. when data write not ready, no data are written to it. 0: not-ready 1: ready 2 r/w 0x0 rx fifo3 ready write 1 to this register when data write is ready. the register is set to 0 upon completion of writing to the fifo. when data write not ready, no data are written to it. 0: not-ready 1: ready 1 r/w 0x0 rx fifo2 ready write 1 to this register when data write is ready. the register is set to 0 upon completion of writing to the fifo. when data write not ready, no data are written to it. 0: not-ready 1: ready 0 r/w 0x0 rx fifo1 ready write 1 to this register when data write is ready. the register is set to 0 upon completion of writing to the fifo. when data write not ready, no data are written to it. 0: not-ready 1: ready cdin_set4 rx fifo1 start address setting offset : 0x10 , reset : 0x00 bits name direction reset description 31:0 r/w 0x0 rx fifo1 start address setting setting to [1:0] byte is ignored, and [1:0] byte is set to x00. cdin_set5 rx fifo1 size setting offset : 0x14 , reset : 0x400 bits name direction reset description 11:0 r/w 0x400 rx fifo1 size setting this register is used to set fifo size. when the amount of data written to ram reaches the set value, a termination interrupt is generated to start writing data to the subsequent fifo. cdin_set6 rx fifo2 start address setting offset : 0x18 , reset : 0x00 bits name direction reset description 31:0 r/w 0x0 rx fifo2 start address setting setting to [1:0] byte is ignored, and [1:0] byte is set to x00. cdin_set7 rx fifo2 size setting offset : 0x1c , reset : 0x400 bits name direction reset description 11:0 r/w 0x400 rx fifo2 size setting this register is used to set fifo size. when the amount of data written to ram reaches the set value, a termination interrupt is generated to start writing data to the subsequent fifo. downloaded from: http:///
177/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 cdin_set8 rx fifo3 start address setting offset : 0x20 , reset : 0x00 bits name direction reset description 31:0 r/w 0x0 rx fifo3 start address setting setting to [1:0] byte is ignored, and [1:0] byte is set to x00. cdin_set9 rx fifo3 size setting offset : 0x24 , reset : 0x400 bits name direction reset description 11:0 r/w 0x400 rx fifo3 size setting this register is used to set fifo size. when the amount of data written to ram reaches the set value, a termination interrupt is generated to start writing data to the subsequent fifo. cdin_set10 rx fifo4 start address setting offset : 0x28 , reset : 0x00 bits name direction reset description 31:0 r/w 0x0 rx fifo4 start address setting setting to [1:0] byte is ignored, and [1:0] byte is set to x00. cdin_set11 rx fifo4 size clock selector setting offset : 0x2c , reset : 0x400 bits name direction reset description 11:0 r/w 0x400 rx fifo4 size setting this register is used to set fifo size. when the amount of data written to ram reaches the set value, a termination interrupt is generated to start writing data to the subsequent fifo. cdin_set12 connection setting offset : 0x30 , reset : 0x80 bits name direction reset description 7 r 0x1 connection operation invalid status 6 r 0x0 data match connection start status 5 r 0x0 data match status 4 r 0x0 connection data under comparison 3:1 r/w 0x0 connection operation mode setting 0: 3 pair data connection 1: 2 pair data connection (data0 and data1) 2: 2 pair data connection (data1, data2) 4: 1 pair data connection (data0) 5: 1 pair data connection (data1) 6: 1 pair data connection (data2) 0 r/w 0x0 connection operation start setting 0: off 1: on cdin_set13 connection data 0 setting offset : 0x34 , reset : 0x00 bits name direction reset description 31:0 r/w 0x0 connection data 0 setting connection setting of last data (i.e., the latest data) out of 3 pair data make setting with {r ch[15:0], l ch[15:0]}. downloaded from: http:///
178/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 cdin_set14 connection data 1 setting offset : 0x38 , reset : 0x00 bits name direction reset description 31:0 r/w 0x0 connection data 1 setting connection setting of the middle data (i.e., data one before the latest) out of 3 pair data. make setting with {r ch[15:0], l ch[15:0]}. cdin_set15 connection data 2 setting offset : 0x3c , reset : 0x00 bits name direction reset description 31:0 r/w 0x0 connection data 2 setting connection setting of the first data (i.e., data two before the latest) out of 3 pair data. make setting with {r ch[15:0], l ch[15:0]}. cdin_set16 ecc/edc setting offset : 0x040 , reset : 0x0e0000 bits name direction reset description 20:16 wait_busreq r/w 0x0e ahb bus request wait cycle sets the value of wait cycle upon issuance of hbusreq (set value ? 2) ? 2 sysclk. the default is 32 sysclk cycles. 15:12 max_pq_cnt r/w 0x0 number of correction times: 0 to 15 times 11:9 - 8 porq r/w 0x0 order of state p and state q 0: from state p 1: from state q 7:6 - 5:4 edcmode r/w 0x0 edc mode 1: mode1 2: mode2 form1 3: mode2 form2 3 - 2 dmaon r/w 0x0 dma on/off for ecc/edc 0: off 1: on 1 eccon r/w 0x0 ecc on/off 0: ecc off 1: ecc on 0 edcon r/w 0x0 edc on/off 0: edc off 1: edc on cdin_set17 ecc/edc dma start address setting offset : 0x44 , reset : 0x00 bits name direction reset description 19:0 r/w 0x0 ecc/edc dma start address setting lower 2 bits are set to 2b00. place sector data according to 4-byte boundary. eccstart ecc start offset : 0x048 , reset : 0x0 bits name direction reset description 0 w D ecc starts up by write access. edcstart edc start offset : 0x04c , reset : 0x0 bits name direction reset description 0 w D edc starts up by write access. downloaded from: http:///
179/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 irq_set0 irqmask setting offset : 0x60 , reset : 0xffff bits name direction reset description 15:12 r/w 0xf rx fifo4 to 1 sector status interrupt mask 0: no mask 1: mask interrupt 11 r/w 0x1 - 10 r/w 0x1 subq data acquisition completion interrupt mask 0: no mask 1: mask interrupt 9 r/w 0x1 cd-text data acquisition completion interrupt mask 0: no mask 1: mask interrupt 8 r/w 0x1 edc termination interrupt mask 0: no mask 1: mask interrupt 7 r/w 0x1 ecc termination interrupt mask 0: no mask 1: mask interrupt 6 r/w 0x1 bfullo interrupt mask when the bfullo signal level rises to h: 0: no mask 1: mask interrupt 5 r/w 0x1 rx error 2 interrupt mask when data is written even if the amount of data has reached the set maximum fifo size: 0: nomask 1: mask interrupt 4 r/w 0x1 rx error 1 interrupt mask when data is written even if the fifo register is in full status: 0: no mask 1: mask interrupt 3 r/w 0x1 rx fifo4 termination interrupt mask 0: no mask 1: mask interrupt 2 r/w 0x1 rx fifo3 termination interrupt mask 0: not mask 1: mask interrupt 1 r/w 0x1 rx fifo2 termination interrupt mask 0: no mask 1: mask interrupt 0 r/w 0x1 rx fifo1 termination interrupt mask 0: no mask 1: mask interrupt downloaded from: http:///
180/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 irq_set1 irqclear setting offset : 0x64 , reset : 0x0000 bits name direction reset description 15:12 r/w 0x0 rxfifo4 to 1 sector status interrupt clear the interrupt is cleared when 1 is written. the signal level becomes high only for one cycle. 11 r/w 0x0 - 10 r/w 0x0 subq data acquisition completion interrupt clear the interrupt is cleared when 1 is written. the signal level becomes high only for one cycle. 9 r/w 0x0 cd-text data acquisition completion interrupt clear the interrupt is cleared when 1 is written. the signal level becomes high only for one cycle. 8 r/w 0x0 edc termination interrupt clear the interrupt is cleared when 1 is written. the signal level becomes high only for one cycle. 7 r/w 0x0 ecc termination interrupt clear the interrupt is cleared when 1 is written. the signal level becomes high only for one cycle. 6 r/w 0x0 bfullo interrupt clear when the bfullo signal level rises to h: the interrupt is cleared when 1 is written. the signal level becomes high only for one cycle. 5 r/w 0x0 rx error 2 interrupt clear when data is written even if the data amount has reached the set maximum fifo size: the interrupt is cleared when 1 is written. the signal level becomes high only for one cycle. 4 r/w 0x0 rx error 1 interrupt clear when data is written even if the fifo register is in a full status: the interrupt is cleared when 1 is written. the signal level becomes high only for one cycle. 3 r/w 0x0 rx fifo4 termination interrupt clear the interrupt is cleared when 1 is written. the signal level becomes high only for one cycle. 2 r/w 0x0 rx fifo3 termination interrupt clear the interrupt is cleared when 1 is written. the signal level becomes high only for one cycle. 1 r/w 0x0 rx fifo2 termination interrupt clear the interrupt is cleared when 1 is written. the signal level becomes high only for one cycle. 0 r/w 0x0 rx fifo1 termination interrupt clear the interrupt is cleared when 1 is written. the signal level becomes high only for one cycle. downloaded from: http:///
181/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 irq_set2 irq monitor offset : 0x68 , reset : 0xffff bits name direction reset description 15:12 r 0xf rx fifo4 to 1 sector status interrupt 0: interrupt generated 1: interrupt not generated 11 r 0x1 - 10 r 0x1 subq data acquisition completion interrupt 0: interrupt generated 1: interrupt not generated 9 r 0x1 cd-text data acquisition completion interrupt 0: interrupt generated 1: interrupt not generated 8 r 0x1 edc termination interrupt 0: interrupt generated 1: interrupt not generated 7 r 0x1 ecc termination interrupt 0: interrupt generated 1: interrupt not generated 6 r 0x1 bfullo interrupt this interrupt is generated when the bfullo signal level rises to h. 0: interrupt generated 1: interrupt not generated 5 r 0x1 rx error 2 interrupt this interrupt is generated when data is written even if the data amount has reached the set maximum fifo size. 0: interrupt generated 1: interrupt not generated 4 r 0x1 rx error 1 interrupt this interrupt is generated when data is written even if the fifo register is in a full status. 0: interrupt generated 1: interrupt not generated 3 r 0x1 rx fifo4 termination interrupt 0: interrupt generated 1: interrupt not generated 2 r 0x1 rx fifo3 termination interrupt 0: interrupt generated 1: interrupt not generated 1 r 0x1 rx fifo2 termination interrupt 0: interrupt generated 1: interrupt not generated 0 r 0x1 rx fifo1 termination interrupt 0: interrupt generated 1: interrupt not generated moni1 monitor 1 setting offset : 0x80 , reset : 0x280 bits name direction reset description 31:28 r 0x0 0 27:16 r 0x0 previous receive count 15:12 r 0x0 0 11:10 r 0x0 0 9 r 0x1 bfullo 8 r 0x0 datavalid 7 r 0x1 rx fifo empty 6 r 0x0 rx fifo full 5 r 0x0 rx fifo error2 4 r 0x0 rx fifo error1 3 r 0x0 0 2 r 0x0 rx finish 1:0 r 0x0 current fifo no. downloaded from: http:///
182/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 moni2 monitor 2 setting offset : 0x84 , reset : 0x0 bits name direction reset description 31:28 r 0x0 - 27:16 r 0x0 write pointer 15:12 r 0x0 - 11:0 r 0x0 read pointer moni3 monitor 3 setting offset : 0x88 , reset : 0x3ff0080 bits name direction reset description 31:26 r 0x0 0 25:16 r 0x3ff number of counts in sector 15:13 r 0x0 count state in sector 12 r 0x0 sector end 11 r 0x0 good sector 10 r 0x0 interpolation sector 9 r 0x0 back-gate sector 8 r 0x0 short sector 7 r 0x1 open status 6 r 0x0 sync pattern detection 5 r 0x0 sync pattern detection 4 r 0x0 sync pattern detection 3:0 r 0x0 sector state moni3b monitor 3b sector status monitor offset : 0x8c , reset : 0x00 bits name direction reset description 15:12 r 0x0 rx fifo4 sector status 11:8 r 0x0 rx fifo3 sector status 7:4 r 0x0 rx fifo2 sector status 3:0 r 0x0 rx fifo1 sector status 0x5:sync lost (state0 ->open) 0x4:interpolation sector 0x3: back-gate sector 0x2:good sector 0x1: short sector 0x0: undecided downloaded from: http:///
183/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 moni4 cd-rom ecc status offset : 0x90 bits name direction reset description 27 ecc_busy r ecc busy flag 26:23 ecc_state r cd-rom ecc state 22:18 p_state r cd-rom ecc p state 17:13 q_state r cd-rom ecc q state 12 pq_corr_flag r correction made to state p/q (correction to state p/q was made during execution of data correction) 11 pq_uncorr_fl ag r uncorrectable state p/q detected (data including uncorrectable state p/q was detected during execution of data correction) 10 pucf_flag r uncorrectable state p detected 1b0: no uncorrectable data detected 1b1: uncorrectable data detected (uncorrectable data was detected during the last correction to state p) 9 qucf_flag r uncorrectable state q detected 1b0: no uncorrectable data detected 1b1: uncorrectable data detected (uncorrectable data was detected during the last correction to state q) 8 pqucf_flag r uncorrectable data detected after completion of data correction 1b0: no uncorrectable data detected 1b1: uncorrectable data detected (uncorrectable data was detected during the last correction to state p/q) 7 pquc1_flag r uncorrectable data detected during the first data correction 1b0: no uncorrectable data detected 1b1: uncorrectable data detected (uncorrectable data was detected during the first correction to state p/q) 6:4 pqc1_num r number of times of corrections made during the first correction to state p/q 3 pquc2_flag r uncorrectable data detected during the second data correction 1b0: no uncorrectable data detected 1b1: uncorrectable data detected (uncorrectable data was detected during the second correction to state p/q) 2:0 pqc2_num r number of times of corrections made during the second correction to state p/q moni5 cd-rom edc status offset : 0x94 bits name direction reset description 5 edc_busy r edc busy flag 4:1 edc_state r cd-rom edc state 0 edc_flag r edc result 1b0: ok 1b1: ng inreq input request offset : 0x98 , reset : 0x0 bits name direction reset description 0 inreq r/w 0x0 inreq flag 1b0: write disabled 1b1: write enabled downloaded from: http:///
184/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 subq1 subq data acquisition register 1 offset : 0x9c , reset : 0x00000000 bits name direction reset description 31:0 subq [95:64] r 0x0000 0000 subq data [95:64] subq2 subq data acquisition register 2 offset : 0xa0 , reset : 0x00000000 bits name direction reset description 31:0 subq [63:32] r 0x0000 0000 subq data [63:32] subq3 subq data acquisition register 3 offset : 0xa4 , reset : 0x00000000 bits name direction reset description 31:0 subq [31:0] r 0x0000 0000 subq data [31:0] cd-text1 cd-text data acquisition register 1 offset : 0xa8 , reset : 0x00000000 bits name direction reset description 31:0 cd-text [143:112] r 0x0000 0000 cd-text data [143:112] cd-text2 cd-text data acquisition register 2 offset : 0xac , reset : 0x00000000 bits name direction reset description 31:0 cd-text [111:80] r 0x0000 0000 cd-text data [111:80] cd-text3 cd-text data acquisition register 3 offset : 0xb0 , reset : 0x00000000 bits name direction reset description 31:0 cd-text [79:48] r 0x0000 0000 cd-text data [79:48] cd-text4 cd-text data acquisition register 4 offset : 0xb4 , reset : 0x00000000 bits name direction reset description 31:0 cd-text [47:16] r 0x0000 0000 cd-text data [47:16] cd-text5 cd-text data acquisition register 5 offset : 0xb8 , reset : 0x0000 bits name direction reset description 15:0 cd-text [15:0] r 0x0000 cd-text data [15:0] chansel input channel setting register offset : 0xbc , reset : 0x0 bits name direction reset description 1:0 chansel r/w 0x0 i2s input channel setting 0x3: cd-dsp 0x2: channel2 (pad) 0x1: channel1 (pad) 0x0: cd-dsp downloaded from: http:///
185/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 16. i2s output i/f 16.1. features 2.1-ch digital audio output (l-ch ? r-ch ? adc) supports output in i2s/eiaj format selectable sampling rate from 32 khz, 44.1 khz, 48 khz, 88.2 khz, 96 khz, 176.4 khz, and 192 khz (when adc input outputs it, the support of only 32k, 44.1k, 48k) selectable data width from 16, 24, and 32 bits supports bit clock of 64fs supports pitch control (0.5 ? to 2.0 ? in 25 steps) 16.2. description 16.2.1. block diagram the following figure shows an i2s output controller block diagram. ldata_irdata_i lrck_o bck_o data1_o i2s eiaj output mclk_o clk22m_i clk24m_i a_dat reb_o data2_o apb to each block sdram dma i/f out fifo audio data read clock selector to each block bus i/f adc adc data read interpolate filter (pitch control) interpolate filter (adc) dac i/f clk16m_i figure 69. i2s output controller block diagram downloaded from: http:///
186/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 16.2.2. dma i/f the dma i/f block acquires input data fr om ram and has four built-in fifo areas. write data inputted in ram according to the formats shown in the table below. (the formats shown are that in the tx0 area.) four transfer areas, tx0 to tx3 can be set in ram. monaural dat a interpolates rch data with hardware. the upper limit in each area for both stereo and monaural data is 1024 samples. when the last address is read, irq is generated. if the subsequent transfer area is ready, data is transferred to the subsequent area according to the setting of the tx fs register. dma transfer repeats the cycle of tx0 tx1 tx2 tx3 tx0 ?? for 16-bit stereo data: address data[31:16] data[15:0] tx0startaddr r(0) l(0) 4 r(1) l(1) 8 r(2) l(2) : : : + tx0size *4 r(tx0size) l(tx0size) for 24-bit stereo data: address data[31:24] data[23:16] data[15:8] data[7:0] tx0startaddr r(0) l(0) 4 l(1) r(0) 8 r(1) l(1) : : : : : + tx0size *6 + 2 r(tx0size) l(tx0size) for 32-bit stereo data: address data[31:0] tx0startaddr l(0) 4 r(0) 8 l(1) 12 r(1) : : + tx0size *8 l(tx0size) + tx0size *8 + 4 r(tx0size) downloaded from: http:///
187/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 for 16-bit monaural data (when the number of samples is an odd number.): address data[31:16] data[15:0] tx0startaddr l(1) l(0) 4 l(3) l(2) 8 l(5) l(4) : : : + tx0size *2 - l(tx0size) for 24-bit monaural data (when the number of samples is an odd number.): address data[31:24] data[23:16] data[15:8] data[7:0] tx0startaddr l(1) l(0) 4 l(2) l(1) 8 l(3) l(2) : : : : : + tx0size *3 + 2 - l(tx0size) for 32-bit monaural data (when the number of samples is an odd number.): address data[31:0] tx0startaddr l(0) 4 l(1) 8 l(2) : : + tx0size *4 l(tx0size) linear interpolation allows 2x and 4x interpolation. the following table shows corresponding frequencies. 1x (dmaintpsel ? 0) 2x (dmaintpsel ? 1) 4x (dmaintpsel ? 2) 32 khz 16 khz 8 khz 48 khz 24 khz 12 khz 44.1 khz 22.05 khz 11.025 khz downloaded from: http:///
188/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 16.2.3. clock selector the clock selector block is used to generate mclk frequency and consists of three types of clock input, dividers, and selectors. the mclk frequencies can be generated by a combination of clock input and divider. divider 1 2 4 clock source (mhz) 49.152 49.152 24.576 12.288 45.1584 45.1584 22.5792 11.2896 16.9344 16.9344 8.4672 4.2336 the following table shows combinations of sampling rates and mclk frequencies of corresponding sound source. mclk fs 64fs 128fs 192fs 256fs 384fs 512fs 768fs music source fs 32 - - - - 12.288 - 24.576 44.1 - - - 11.2896 16.9344 22.5792 - 48 - - - 12.288 - 24.576 - 88.2 - 11.2896 16.9344 22.5792 - - - 96 - 12.288 - 24.576 - - - 176.4 11.2896 22.5792 - - - - - 192 12.288 24.576 - - - - - 16.2.4. i/o bus interface the i/o bus interface is used to make settings for audio data output from the i/o bus and for digital audio interface. for details, refer to information in the chapter on registers. 16.2.5. audio data read (i2s) when an audio data read request signal data_reb_o is outputt ed to the output fifo, l-channel audio data ldata_i and r-channel audio data rdata_i are inputted from the dma i/f. then, this block is used to make data read timing adjustment (0.5 ? to 2.0 ? in 12 steps) according to the pitch control setting. 16.2.6. interpolating filter the interpolating filter is used to interpolate sample data when the pitch control is set to 0.5x to 1.0x. downloaded from: http:///
189/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 16.2.7. audio data read (adc) the downstream register in the adc block reads data to output it to the interpolating filter (adc). when the sampling frequency of the sound source is set to 32, 44.1, or 48 khz, data is acquired at the same timing as that of audio data read (i2s). bigger sampling frequency than 48khz isn't being supported. the following table shows combinations of the sampling frequencies of sound source and frequencies at which the audio data read (adc) block acquires data. audio data read (adc) data read frequency music source fs 32khz 32khz 44.1khz 44.1khz 48khz 48khz 16.2.8. dac i/f the dac interface is used to output data in i2s/eiaj format. data inputted from sdram and adc are simultaneously outputted. 16.2.9. output waveforms figure 70. i2s output timing (64fs) figure 71. eiaj output timing(64fs) 13 12 15 14 11 8 7 10 9 6 3 2 5 4 1 0 13 12 15 14 lrck bck(64fs) data left channel right channel 13 12 15 14 11 8 7 10 9 6 3 2 5 4 1 0 1 0 2 lrck bck(64fs) data left channel right channel downloaded from: http:///
190/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 16.3. i/o signals pin name i/o function destination clk_i in apb bus clock clkctr rstb_i in reset (active low) rstgen paddr_i in apb bus address apb penable_i in apb bus enable apb pwdata_i in apb bus write data apb pwrite_i in apb bus write enable apb psel_i in apb bus selector apb prdata _o out apb bus read data apb daout_test_mode_i in test mode input - daout_test_ctr_i in test mode register setting - hgrant_i in master x bus grant pdmac ahb hrespm_i[1:0] in ram transport response pdmac ahb hreadymi_i in ram transport finish pdmac ahb hrdatam_i in ram read data pdmac ahb hbusreq_o out master x bus request pdmac ahb htrans_o[1:0] out master x transport type pdmac ahb hsize_o[1:0] out master x transport size pdmac ahb hwrite_o out master x transport direction pdmac ahb haddr_o[19:0] out master x address pdmac ahb hwdata_o[31:0] out master x write data pdmac ahb lrck_o out lr clock output pad bck_o out bit clock output pad data1_o out data output pad data2_o in data output (adc) pad mclk_o out master clock output pad downloaded from: http:///
191/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 16.4. register 16.4.1. memory map name description address offset width reset dacif_set0 control 0x00 8 8h00 dacif_set1 output format setting 0x04 8 8h72 dmacirq dma interrupt 0x2c 32 32h00000000 dmairqclr dma interrupt clear 0x30 8 - sdmairqmsk dma interrupt mask 0x34 4 4hff tx0startaddr dma tx0 start address 0x38 32 32h00000000 tx0size dma tx0 buffer size 0x3c 16 16h0000 tx0fs dma tx0 sampling frequency setting 0x40 16 16h0000 tx0ok dma tx0 transfer ready ok 0x44 8 16'h0000 tx1startaddr dma tx1 start address 0x48 32 32h00000000 tx1size dma tx1 buffer size 0x4c 16 16h0000 tx1fs dma tx1 sampling frequency setting 0x50 16 16h0000 tx1ok dma tx1 transfer ready ok 0x54 8 16'h0000 tx2startaddr dma tx2 start address 0x58 32 32h00000000 tx2size dma tx2 buffer size 0x5c 16 16h0000 tx2fs dma tx2 sampling frequency setting 0x60 16 16h0000 tx2ok dma tx2 transfer ready ok 0x64 8 16'h0000 tx3startaddr dma tx3 start address 0x68 32 32h00000000 tx3size dma tx3 buffer size 0x6c 16 16h0000 tx3fs dma tx3 sampling frequency setting 0x70 16 16h0000 tx3ok dma tx3 transfer ready ok 0x74 8 16'h0000 fsseqstart dma transport start setting 0x78 8 8h00 fsseqstop dma transport abort setting 0x7c 8 8b00 softreset software reset 0x80 8 - dmaflag dma flag monitor 0x84 10 8h01 outfifoflash out fifo flash 0x88 1 16h0000 outfifohold out fifo hold setting 0x8c 1 16'h0000 outfifoflag out fifo full / empty flag 0x90 12 16'h0001 downloaded from: http:///
192/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 16.4.2. register detail dacif_set0 offset: 0x00 width: 8 bits bits name direction reset description 3 din_test r/w 0x0 (reserved) 2 adcout_on r/w 0x0 adc if block on/off 0: off 1: on 1 pause_on r/w 0x0 dac if block pause setting this register to 1 disables data to receive/transmit between outfifo and audrd. 0: normal operation 1: pause 0 daout_on r/w 0x0 dac if block on/off setting this register to off fix output of lrck, bck, and data to l level and disables data to receive/transmit between outfifo and audrd. 0: off 1: on dacif_set1 offset: 0x04 width: 8 bits bits name direction reset description 6:0 r/w 0x72 output format selection 0x72: i2s 64fs format 0x02: eiaj 64fs format downloaded from: http:///
193/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 dacif_set8 offset: 0x20 width: 16 bits bits name direction reset description [13:9] pitchctrl r/w 0x00 pitch controller varies pitches in halftone steps of the equal temperature of 12 degrees. x0.5 C x2.0 25step 10100; x0.5 10101; x0.5229 10110; x0.5612 10111; x0.5946 11000; x0.6299 11001; x0.6674 11010; x0.7071 11011; x0.7491 11100; x0.7937 11101; x0.8407 11110; x0.8908 11111; x0.9438 00000; x1.0 00001; x1.0594 00010; x1.1224 00011; x1.1892 00100; x1.2599 00101; x1.3348 00110; x1.4142 00111; x1.4983 01000; x1.5874 01001; x1.6817 01010; x1.7817 01011; x1.1887 01100; x2.0 [8:5] adc_atten r/w 0x0 adcrd data input attenuation attenuates data input from adc data input is variable in 16 stages in steps of 6db. 0x0: 0db 0x1: ? 6db 0xf: ? 90db [4:0] audrd_atten r/w 0x0 audrd data input attenuation attenuates data input from sdram data input is variable in 32 stages in steps of 6db. 0x0: 0db 0x1: ? 6db 0x1f: ? 190db downloaded from: http:///
194/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 dacif_set9 offset: 0x24 width: 4 bits bits name direction reset description 2 start_clksel r/w 0x0 clock selection start selects clock according to th e clk_sel register setting. when the clk_sel register setting is completed, write h to this register. (detects the signal at the rising edge) 1:0 clk_sel r/w 0x0 clock domain setting makes clock setting to output i2s select a sampling frequency for sound source to be played back. 0: 16.9344mhz 1: 45.1584mhz (fs ? 44.1, 88.2, 176.4 khz) 2: 49.152mhz (fs ? 32, 48, 96, 192 khz) dacif_set10 offset: 0x28 width: 8 bits bits name direction reset description 4 start_clksel _mclk r/w 0x0 clock select start selects mclk according to the clk_se_mclk and div_sel_mclk register settings. when the clk_se_mclk and div_sel_mclk register settings are completed, write h to this register. (detects the signal at the rising edge) 3:2 div_sel_m clk r/w 0x0 mclk clock division setting 0: mclk masked 1: 1 2: 1/2 3: 1/4 1:0 clk_sel_m clk r/w 0x0 mclk clock domain setting 0: 16.9344 mhz 1: 45.1584 mhz 2: 49.152 mhz downloaded from: http:///
195/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 dmairq offset: 0x2c width: 32 bits bits name direction reset description 31:4 r 0x0 - 3 outfifo_erro r r 0x0 generated on receipt of read request from dac if when outfifo is set to empty. the last data is continually outputted until outfifo_flash is executed. 0: no interrupt generated 1: interrupt generated 2 outfifo_em pty r 0x0 generated when outfifo is set to empty 0: no interrupt generated 1: interrupt generated 1 r 0x0 - 0 dma_final r 0x0 generated when the last data is read from dma 0: no interrupt generated 1: interrupt generated dmairqclr offset: 0x30 width: 8 bits bits name direction reset description 3:0 dmairqclr w - dma interrupt clear writing 1 to this register clears the corresponding bit of dmairq. since the bit is continualy cleared during 1 is written to the register, write 0 to it after clearing the bit. dmairqmsk offset: 0x34 width: 8 bits bits name direction reset description 3:0 dmairqmsk r/w 0xf dma interrupt cause mask (0: unmasked, 1: masked) masks the cause of interrupt of the corresponding bit of dmairq tx0startaddr offset: 0x38 width: 32 bits bits name direction reset description 32:0 tx0startadd r r/w 0x0000 dma tx0 start address (specifies the start address as absolute address) tx0size offset: 0x3c width: 16 bits bits name direction reset description 11:0 tx0size r/w 0x000 dma tx0 buffer size (specifies sample number ? 1 up to a maximum of 1024 samples for l and r, respectively) downloaded from: http:///
196/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 tx0fs offset: 0x40 width: 8 bits bits name direction reset description 7:5 dmaif_fs r/w 0x0 sampling frequency setting 0: 32 khz 1: 44.1 khz 2: 48 khz 3: 88.2 khz 4: 96 khz 5: 176.4 khz 6: 192 khz 7: reserved note: the output sampling frequency of dacif should follow the set value of this bit. apply the same to dma interpolation. 4:3 dmaif_datawidth r/w 0x0 bit width setting 0: 16 bits 1: 24 bits 2: 32 bits 2 dmaif_mono r/w 0x0 monaural interpolation setting 0: stereo data 1: interpolated monaural data 1:0 dmaif_intp_sel r/w 0x0 dma interpolation setting 0: 1 (32 khz, 48 khz, 44.1 khz) 1: 2 (16 khz, 24 khz, 22.05 khz) 2: 4 (8 khz, 12 khz, 11.025 khz) tx0ok offset: 0x44 width: 8 bits bits name direction reset description 0 tx0ok r/w 0x0 write 1 to this bit when tx0 is ready. when 0 is written, dma disables data acquisition. when data read for the set value of tx0size is completed or suspended by fsseqstop, this bit is set to 0. note: the operation of the following registers conforms to that of the tx0 register aforementioned. dma transfer repeats the cycle of tx0 tx1 tx2 tx3 tx0 ?? tx1startaddr, tx1size, tx1fs, tx1ok (offset:; 0 x 48 to 0x54) tx2startaddr, tx2size, tx2fs, tx2ok (offset:; 0 x 58 to 0x64) tx3startaddr, tx3size, tx3fs, tx3ok (offset:; 0 x 68 to 0x74) downloaded from: http:///
197/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 dmaseqstart offset: 0x78 width: 16 bits bits name direction reset description 0 w 0x0 dma transfer start setting (starts dma transfer operation when write to the corresponding address is detected. note: the transfer is accepted when the dma programmable controller is in an idle state and the subsequent transfer area is ready.) dmaseqstop offset: 0x7c width: 16 bits bits name direction reset description 0 w 0x0 forced dma transfer stop setting (stops dma transfer operation when write to the corresponding address is detected during dma transfer is in progress.) softreset offset: 0x80 width: 16 bits bits name direction reset description 0 w 0x0 software resetting initializes the dma-fs switching programmable controller and flashes outfifo when write to the corresponding address is detected. note: all writable i/o registers return to their default to clear interrupts. dmaflag offset: 0x84 width: 16 bits bits name direction reset description 6:4 seq_cnt r 0x0 status monitor of fs switching programmable controller 0: idle 1: transfer 2: continue 3: ready 4: stop 3:2 current_tx r 0x0 indicates currently busy transfer area number: tx fifo(tx0 to tx3) note: since this number is updated when switching or stopping data transfer, the subsequent transfer area number is indicated during data transfer stops. 1 dma_full r 0x0 set to 1 when fifo in dmaif is full. 0 dma_empty r 0x1 set to 1 when fifo in dmaif is empty. downloaded from: http:///
198/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 outfifoflash offset: 0x88 width: 16 bits bits name direction reset description 0 r/w 0x0 initializes the dma-fs switching programmable controller and flashes outfifo when write to the corresponding address is detected. note: all writable i/o registers return to their default to clear interrupts. outfifohold offset: 0x8c width: 16 bits bits name direction reset description 0 r/w 0x0 outfifo preamble hold setting (0: preamble hold off, 1: preamble hold on) makes setting of data to be outputted on receipt of read request from dac if when outfifo is empty when preamble hold is set to on, the last data is outputted. when it is set to off, all 0 data is outputted. dmaflag offset: 0x90 width: 16 bits bits name direction reset description 1 outfifo_full r 0x0 set to 1 when outfifo is full. 0 outfifo_empty r 0x1 set to 1 when outfifo is empty. downloaded from: http:///
199/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 17. cd servo controller 17.1. features supports rotation speed of cd up to 4 ? built-in preservo amplifier with power save mode supports playback of cd-rw allows independent offset adjustment of ac, bd, e, and f amplifiers built-in auto tracking and focus adjustment function built in pll and clv with a wide lock range built-in asymmetry correction function 17.2. description 17.2.1. block diagram the following figure shows a cd-dsp block diagram. rf signal gen (analog) digital servo signal processor window ecc sram 128x32 sram 2048x8 bus i/f command i/f cd driver cd p/u apb sub-q i/f audio data clk16m_i lrck_o bck_o data_o subsyq_o wfck_o subck_i subdata_o monitor clk88_o figure 72. cd-dsp block diagram downloaded from: http:///
200/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 17.2.2. window if a signal is regenerated, the frame sync signal may not be detec ted due to a disc flaw or jitter, or other signals may be detected in error as a sync signal. if any sync signal is detected in error, all other signals will also be detected as a sync signal. this requires eliminating these wrong sync signal s and generating new sync signals. consequently, the window block internally executes the following operation: (1) detect sync signals: 11t, 11t, 2t (hereinafter called sync); (2) generate from sync a signal that is set to h level after plck counts 588 (hereinafter called 588t); (3) set a ? 9-count window with plck to 588t; and (4) if sync is detected in this window, regard it as a correct sync signal. if sync is not detected there, use 588t as sync up to 13 successive frames. if sync is not detected in 13 or more successive frames, open t he window to use sync detected first after that as a correct sync signal. in this case, if no sync signal is obtained from disc in 3 successive frames, open the window again. downloaded from: http:///
201/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 17.2.3. error detection and correction (ecc) block the ecc block executes de-interleaving function and double c1/quad c2 error detection, correction, and flag processing. the correction capability is selectable with the command &ha1[4]. a super strategy is used for flag processing up to the double c1 and double c2 correction. triple c2 correction is executed when there are three points to which no c1 correction can be made. quad c2 correction is executed when there are found points to which no c1 correction can be made. the ecc block also enables corrections to the efm conversion table. this makes it possible to automatically correct t2 erroneously detected by switching the command &hab[0] as t3. 16-kbit sram is used to absorb jitters for ? 4 frames. the frame counter is reset during tracking jump. the ecc block supports cd-da and cd-rom modes selectable by the command &ha1[6]. the ecc block has the built-in mute and attenuation functions that are set by the command &ha0[5:4]. the function to automatically turn on the mute function when the frame counter overflows is selectable by the comm and &ha1[5]. the ecc function supports normal mode and wide mode selectable by the command &h82[5:4]. table 17.2.3.0 control commands in ecc block setting item command error correction capability &ha1[4] cd-da / cd-rom mode &ha1[6] audio mute / ? 12db attenuation &ha0[5:4] audio mute when the frame counter overflows &ha1[5] normal / wide mode &h82[5:4] table 17.2.3.1 c1 group flags in ecc block c1f1 c1f2 c1 group error correction status 0 0 no error 1 0 single c1 correction succeeded correction 0 1 double c1 correction succeeded correction 1 1 c1 correction disabled table17.2.3.2. c2 group flags in ecc block c2f1 c2f2 c2f3 c2fx c2 group error correction status 0 0 0 0 no error 1 0 0 0 single c2 correction succeeded correction 0 1 0 0 double c2 correction succeeded correction 0 0 1 0 triple c2 correct ion succeeded correction 1 0 1 0 quad c2 correction succeeded correction - - - 1 c2 correction disabled downloaded from: http:///
202/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 17.3. rf signal gen (analog) + digital servo signal processor 1.clv and pll 2.servo-type a/d converter 3.ats comparator 4.tzc comparator 5.cout signal generation 6.basic block of servo filter circuit 7.focus servo filter 8.tracking servo filter 9.thread servo filter 10.servo controller 11.focus search 12.fzc comparator 13.cd-rw detection and gain setting 14.tracking jump 15.tracking half-wave brake mode 16.tracking gain-up mode 17.intermittent thread feed 18.auto-adjustment and measurement 19.flaw detection and countermeasure 20.preservo amplifier 21.yflag generation 22.directions for pattern layout of pcb (recommended) downloaded from: http:///
203/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 17.3.1. clv and pll below diagram shows the clvpll system components. 11t length detector clv velocity counter vco di v1 pc div2 pci counter pll fre q. counter clv phase detector pll target 8bit dac noise shaper clv t arget clv filter (see the next figure) slow /fast 30 p 20k 10k 10k sw2 sw1 efm plck 15k 5k fco pco pll servo clv serv o clv ou t h1 noise shaper fc integrator h5 sw3 pcpi pcni figure 73. clvpll system components downloaded from: http:///
204/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 17.3.2. functional description of each block clv phase detection this block extends the output value from sram frame counter of the ecc by bit extension and thereby generates clv phase error signal. clv speed counter under wide mode, rough mode: this counter count how often efm edge comes during rfck / 64 cycle. under speed phase mode: this counter count how often plck comes during rfck cycle. difference between the counted value by this counter and clv target value is output as clv speed error signal. sw3, sw1 either one is selected according to actual mode. for the detail, refer to the individual functional description of clv and pll. 11t length detection this block counts efm edge to edge length with plck at wfck/4 cycle and measures maximum pulse width (detects pulse peak). the shortest pulse width at wfck/32 cycle is detect ed from these measured values (detection of pulse bottom). under high speed rough mode, pulse peak is detected at wfck/2 cycle and pulse bottom detected at wfck/16 cycle. shift slow/fast to l if counted pulth width value is 11t or less, and shift to h if the width value is larger than 11t. pll frequency counter this block counts the number of plck/36 during rfck/64 cycle. difference between this value and pll target value is output as pll frequency error signal. pci counter this counter counts up when efm edge is earlier than startup of plck/2 and counts down when it is later than startup of plck/2, deeming the value, which is given by &h89 command every rfck cycle, as initial value. coefficient h1 this is set using command &h84[2:0]. coefficient h5 this is set using &h83[2:0] command for pll frequency counter and using &h84[6:4] command for pci counter. sw2 this is for test use, which is isolated by setting command &h63[7:4]=eh and op-amp input data can be output from ana_moni0 terminal. this is to measure fc and pc loop characteristics. div1 this is set using command &h50[7:6]. div2 this is set using command &h50[5:4]. downloaded from: http:///
205/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 vco the overall frequency characteristic of vco can be changed by command &h9e[4:0], and tilt of the same linear characteristic be changed by command &h9f[3:0]. vco frequency &h9f[3:0] &h9e[4:0] vco input voltage figure 74. vco characteristic control clv filter its shows composition of clv filter system. z -1 in low boost through out h2 h3 h4 figure 75. composition of clv filter system coefficient h2 this is set using command &h85[6:4] and &h86[6:4]. coefficient h4 this is set using command &h85[2:0] and &h86[2:0]. coefficient h3 actually this is not coefficient, outputting +1lsb when input value (z -1 ) is positive and outputting -1lsb when it is negative. downloaded from: http:///
206/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 pc this pc is intended for phase comparation of efm edge with plck rise. the diagrams below show the timing chart. (3)case of plck downcame simultaneous with efm edge phase pco pcpi pcni plck efm hi-z h h l efm plck pco pcpi pcni hi-z (2)case of plck downcame faster than efm edge phase. hi-z efm plck pco pcpi pcni h l (1)case of plck downcame later than efm edge phase pco continues to output l until next plck rise from efm edge. and pco outputs h throughout the first section of plck=l after hi-z. output from pco is converted to lpf by built-in r and exterm al c and the sign thereof is inverted by op-amp. for that, vco acts to match both ends of efm with plck downcome. further, when pll is initialized, vco/16 is input in plase of efm, so that same value is output from pco irrespective of positive value or negative value and the initializing function only by fco is validated. furthermore, if efm flaw is detected during usual playback, pc does same operation as initializing to theby prevents plck from deviating greatly from the lock. downloaded from: http:///
207/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 17.3.3. operation mode 17.3.3.1. clv operation mode table 17.3.3.1. summarizes the clv operation mode, setting commands and conditions. operation mode &h80[6:4] setup value &h82[5:4] setup value description off 0 - off. vc is output. kick 1 - &h88[7:0] setup value is output (positive voltage) brake 2 - 2 complement to &h88[7:0] setup value is output. (negative voltage) auto stop 3 - this is the mode to stop disc rotation automatically. at first, the operation mode is shifted to br ake mode and, then, break mode is shifted to off mode when the clv counter counted a value equivalent to 1/15 of usual value. on (auto) 4 0 or 1 the speed mode is autom atically shifted to rough mode against lock=l and to speed phase mode against lock=h. speed phase 5 0 or 1 clv target value is fix ed to 588. the speed counter of clv counts the number of plck during rf ck cycle and dirrerence between the two values is clv speed error value. at the same time, sw3 turns on and phase error value produced upon detection of clv phase is added for control of the disc rotation. rough 6 0 or 1 clv target value increm ents/decrements according to slow/fast signal. when slow/fast signal is l, the disc rotation is recognized as fast and consequently the clv target value decrements. when slow/fast signal is inversely h, the disc rotation is recognized as slow and consequently the target value increments. by this serch operation, the disc rotation is matched with the target value so pll is locked. at this time, sw3 turns off and error component by detection of clv phase is not added. high speed rough 7 0 or 1 under this mode, clv operates similarly to rough mode, but peak-bottom hold cycle for detection of 11t length shortens, which generates slow/fast. this mode is used for search, etc. wide 4 to 7 2 clv target value is set using command &h81. clv speed counter counts similarly to rough mode. this wide mode enables to control the disc to any optional revolutions. table 17.3.3.1 ! ? ? . descroption of clv operation modes downloaded from: http:///
208/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 17.3.3.2. pll operation mode table 17.3.3.2 summarizes the pll operation mode, setting commands and conditions. operation mode &h82[5:4] setting value lock condition description normal initialize 0 - under this mode, sw1 is shifted to pll frequency counter. pll frequency counter counts the number of plck/32 during rfck/64 cycle and aligned pll center frequency to 4.3218mhz. this mode must be selected and executed without fail prior to usual playback. normal pc 1 - under this mode, fco output terminal is held at the value under normal initialize mode. and plck is locked to efm signal by pco output only. this condition is kept in reproducing in normal mode. wide fc 2 l under this mode, sw1 is shifted to pll frequency counter. pll frequency counter counts similarly to counting under normal initial mode, but pll target value increments/decrements according to slow/fast signal and plck frequency is changed so it matches the disc speed, whereby plck is enabled to follow and catch efm frequency. wide pci 2 h under this mode, sw1 is shifted to pci counter. pci counter generates phase difference between efm and plck. by using an integral value determined from this phase difference value as fco output, plck can follow the disc rotation, even if it varies greatly, and continues to keep lock condition over the wide frequency band. in reproducing under wide mode, the pll locks this condition at the frequency equivalent to disc speed of about 0.5 to 4.0 speed. table 17.3.3.2 description of pll operation modes downloaded from: http:///
209/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 17.3.4. a/d converte r for servo system a/d convertor is samples each analog input signal from e, f, ac, bd ad_moni0 and other terminals at time sharing and converts the sampled signals to digital value respectivery. the sampling frequency is 88.2khz and comversion accuracy is 10bit. the conversion d-range is vc 0.4*v dd . the figure below is the input signals connection diagram for the a/d converter. figure 76. input signal connection diagram for servo system adc the converted values from ch0, ch1, ch4 and ch5 are subtracted after conversion, and generate fe signal and te signal. thereafter, these signals converted value ar e always transferred to the sigital servo filter computing unit and used for contro l of each servo unit. as for ch2 and ch3, the input signal is selected by comm and, and the converted value is output from din/dout and transferred to micro computer. for the detailed operation, refer to description of individual operation. alse, figure 767 shows the timing chart. ch5 ch4 ch3 ch2 ch1 4 3 1 0 ch0 e f sel2 ad_moni0 to servo filter 10bit ac bd ad_moni1 ana_moni0 ana_moni1 2 vc sel1 downloaded from: http:///
210/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 adclk_ir adsmp_ih (ch0 sample) (ch1 sample) (ch2 sample) (ch3 sample) (ch4 sample) (ch5 sample) addat_od[9:0] addlat_or[0] addlat_or[1] addlat_or[2] addlat_or[3] addlat_or[4] addlat_or[5] (ch1) (ch0) (ch3) (ch2) (ch5) (ch4) 13cycle 16cycle 13cycle 13cycle 13cycle 13cycle figure 77. servo system adc operating timing chart downloaded from: http:///
211/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 17.3.5. ats comparator the figure below is ats comparator operation block diagram. comp fc = 12 0 hz fc = 3.3hz lim vc v dd 0.00625 &hf3[7:4] te hpf lpf at s figure 78. ats comparator operation diagram for usual playback, the te signal is passed the band path filter and window comparation is excuted for the value. the figure below shows the i/o relation. lim ats in p ut volta g e l h h -v dd 0.00625 &hf3[7:4] v c +v dd 0.00625 &hf3[7:4] figure 79. ats comparator i/o characteristics output from the comparator (lim) is l against the range of vcv dd 0.00625&hf3[7:4] and h against other than this range. when amplitude of ats input signal is wide, output from the comp arator is h, which is deemed as shock detection condition. and tracking gain-up operation is executed to upgrade the anti-shock performance. it is selectable by command &hce[5] whether gain-up is executed or not by ats.and it is selectable by command &h8c [6:4] that gain-up continued time. for the gain-up operation detail, refer to description of tr jump. it is impossible to monitor ats comparator output itself. however, it is possible to do so, though indirect, by validating the anti-shock performance by &hce[5]=0 and by outputting gain-up signal (tguon) from flag2 terminal by &hb0[2:0]=bh. downloaded from: http:///
212/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 17.3.6. tzc comparator tzc comparator is comparator using digital filter and the threshold value thereof is vc. the figure below shows the block diagram comp tzc 0 te hpf figure 80. tzc comparator block diagram the cut-off frequency of hpf is selected by command &hf7[1:0]. output data from the tzc comparator are used to count the number of tr acks in track jumping. these outputs can be monitored from flag2 treminal by command &hb0[2:0]=8h. downloaded from: http:///
213/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 17.3.7. generation of cout signal cout signal is a signal sampled from mirror signal at tzc change point, which is then used to detect moving direction of the pickup and to count the number of tracks. the figure below shows the timing chart for movement of the pickup in outward direction. at this time, tzc and cout come to same phase. figure 81. cout signal-related diagram (when moving outward) the figure below shows the timing chart for movement of the pickup in inward direction. at this time, tzc and cout come to inverce phase to one another. figure 82. cout signal-related diagram (when moving inward) downloaded from: http:///
214/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 17.3.8. basic block of servo filter circuit this block is intended for computation of focus servo filter, tracking servo filter, sled servo filter, and band path filter an d low path filter for auto adjustment, at time sharing. the figure below shows the basic iir filter block composing the filter circuit. figure 83. basic iir filter blocks in servo filter unit this basic iir filter works on sampling frequency 88.2khz and can realize lpf and hpf by changing coefficients a1, b0, b1. of servo filters and auto adjust filters, this basic iir filter is used as lpf, lps and hpf, and 3 different symbols in the abo ve figure are used in the composition diagram for each filter to indicate the respective filter characteristic. downloaded from: http:///
215/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 17.3.9. focus servo filter ac f_loopon 0 fdout ftg hpf lpf f-lps f-bpf f_gairan_on fd_offset gairan 0 f-lpf 0 fsearch sel sel oscg fg flg fb_ac fb_bd bd fe_offset ac_offset b d_o ffse t fhig sel se l fsg fhg sel sel 0 fhpfsel fth rsel fthrof f fhpfoff 0 se l fmu to ns figure 84. focus servo filter block diagram downloaded from: http:///
216/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 input data ac,bd data converted from ac and bd input signal by 10bit ad converter. fe_offset offset value being setup by command &hf6[6:4]. ac_offset, bd_offset offset value being set up by command &h94[7:0] and &h95[7:0], which can be set up by auto adjustment sequence. fb_ac, fb_bd offset value being set up by command &h98[7:0], which set up fe balance by changing ac and bd gain. fd_offset offset value being set up by command &h92[7:0], which can be set up by auto adjustment sequence. f_loopon signal singal to turn on focus loop. at command &hc0[5:4]=1 is used, this signal turns on when the requirements is met upon focus serch. also, when command &hc0[0]=1 is send, focus loop is forcedly turned on. ftg to set up input gain using command &hec[3:2]. disturbance signal disturbance signal for auto adjustment use, being generated by servo controller. not added in usual producing. oscg to set up disturbance level using command &hed[5:0]. this disturbance level must be re-set optimally according to measured data, because it is common with the tracking filter. f_disturbance_on signal add switch for disturbance, which is turned on when measureing focus balance and gain. fg to set up overall gain. command &h9a[5:0] is used for setting up. this gain can be set up per the auto adjust sequence. f-lps portion equivalent to lag lead filter in the conventional model. cut-off and attenuation level are selected using command &he9[7:4]. fsg, fhig coefficient for gain-down operation against defect and new_defect. the operation mode is selectable by command &hd6[7:4] and gain-down level is selectable by command &hef[4]. furthermore, defect mode can be force-selected by command &hc0[1]=1. f-bpf filter unit composed of lpf+hpf, used for high-area phase compensation. peak frequency is selectable by command &he9[1:0]. fhg f-bpf output addition gain, which can be set using command he8[3:0]. f-lpf filter for servo band. cut-off frequency is selected using command &he9[3:2]. flg f-lpf output addition gain, which can be set using command &he8[7:4]. fhpfsel,fthrsel,fhpfoff,fthroff signal switch to hold dc against defect and new_defect. this switch operation is selectable by command &hd6[7:4]. hold system is selectable by command &hd7[5:4]. furthermore, defect mode can be force-selected by command &hc0[1]=1. fsearch signal focus serch voltagel, generated by servo controller. this is fixed to a certain voltage during usual playback. ns this is noise shaper, which can be set using command hef[2]. fmuto signal signal to turn off focus loop. output to fdout terminal via servo 8bit dac. downloaded from: http:///
217/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 17.3.10. tracking servo filter e tmut i 0 tdout tt g hp f lpf t-lps t-bpf t_gairan_on td_offset gairan 0 t-lpf 0 jump sel se l os cg tg tlg gd_e gd_f f te _of fs et e_offset f_offset thig sel sel ts g thg sel sel 0 thpfsel tthrsel tthroff thpfoff 0 sel tmuto n s tdout_offset tb _e tb_f e+f_hpf figure 85. tracking servo filter block diagram downloaded from: http:///
218/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 input data e,f data converted from e and f input signal by 10bit ad converter. te_offset offset value being setup by command &hf6[2:0]. e_offset, f_offset offset value being set up by command &h96[7:0] and &h97[7:0], which can be set up by auto adjustment sequence. tb_e, tb_f offset value being set up by command &h99[7:0], which set up te balance by changing e and f gain. e+f_hpf high pass filter for (e+f) signal. cut-off frequency is selectable by command &hf7[3:2].gain is selectable by command &hf7[7:4]. can be made reversed by command &h8d[0]. gd_e, gd_f it is the gain for the time of gain-down operation.gain-down level is selectable respectively by command &hf8[6:4] and &hf8[2:0]. td_offset offset value being set up by command &h93[7:0], which can be set up by auto adjustment sequence. tmuti signal signal to turn off tracking loop. this signal turns off when the command is &hc1[5:4]=0 or during tr jump, sd move or when f_loopon signal is l. also, when the command is &hc0[0]=1, &hc1[5:4] setup is force-validated. ttg to set up input gain using command &hec[1:0].gain-down level for the time of gain-down operation is selectable by command &hf9[5:4]. disturbance signal disturbance signal for auto adjustment use, being generated by servo controller. not added in usual producing. oscg to set up disturbance level using command &hed[5:0]. this disturbance level must be re-set optimally according to measured data, because it is common with the focus filter. tg to set up overall gain using command &h9b[5:0]. this gain can be set up per the auto adjust sequence. t_disturbance_on signal add switch for disturbance, which is turned on when measureing tracking gain. t-lps it is the portion equivalent to lag lead filter in the conventional model. the cut-off and attenuation level are selected using command &heb[7:4]. tsg, thig it is the coefficient for the time of gain-down operation in the time of gain-up operation or defect and new_defect. high-area gain and through-gain can be changed by changing this gain. the operation mode is selectable by command &hd6[3:0]. the gain- up level is selectable by command &hec[5:4] and gain-down level is selecta ble by command &hec[7;6]. furthermore, defect mode can be force-selected by command &hc0[1]=1. t-bpf filter unit composed of lpf+hpf, used for high-area phase compensation. peak frequency is selectable by command &heb[1:0]. thg t-bpf output addition gain, which can be set using command &hea[3:0]. t-lpf filter for servo band. cut-off frequency is selected using command &heb[3:2]. tlg t-lpf output addition gain, which can be set using command &hea[7:4]. downloaded from: http:///
219/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 thpfsel,tthrsel,thpfoff,tthroff signal switch to hold dc against defect and new_defect. this switch operation is selectable by command &hd6[3:0]. hold system is selectable by command &hd7[6:4]. furthermore, defect mode can be force-selected by command &hc0[1]=1. ns this is noise shaper, which can be set using command &hef[3]. tdout_offset offset value being setup by command &hf9[3:0]. jump signal output selected when tr jump. tmuto signal signal to turn off the tracking loop. this signal turns off during sd move or when the command is &hc1[5:4]=0 or when f_loopon signal is l. also, when the command is &hc0[0]=1, &hc1[5:4] setup is force-validated. output data tdout output to tdout terminal via servo 8bit dac. downloaded from: http:///
220/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 17.3.11. sled servo filter sd_in sdout sd_offset sel sg sled_h sdout_sel[1:0] sled_l s-lps sel smuti 0 0 figure 86. sled servo filter block diagram input data output data from lpf of tracking servo filter. smuti signal signal to turn off the sled loop. sd_offset offset value set up using command &h91[7:0], which can set up per auto adjustment sequence. s-lps lag lead filter. attenuation level can be selected by command &hf5[2:0]. when the command is &hf5[2:0]=0, t he filter comes to lpf, whose cut-off frequency is 188hz. sg sled gain, selectable by command &hf4[7:0]. sled_h, sled_l output selected when the sled moves or multi tr jump or command is &hc1[1:0]=2,3. output value is set up using command hfe[7:4]. sdout_sel signal sled servo control signal, controlled by command &hc1[1:0] of controller. the servo on precondition is &hc1[1:0]=1 and, in addition, gfs88 signal is h. in the case of &hc0[0]=1, &hc1[1:0] setup is force-validated. output data output to sdout terminal via servo 8bit dac. 17.3.12. servo controller this is the control block to control focus search, track jump, sled intermittent feed, auto adjust function, etc. for the detail, refer to the description of each control item. downloaded from: http:///
221/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 17.3.13. focus search 17.3.13.1. focus on operation figure 87. focus on operation timing chart by using command &h60[4]=1, lon terminal gets h to allow laser on and the focus search is started simultaneously. initially f_loopon signal is l and the loop is in off. fsearch voltage reduces once to minimum value (fsmin) and thereafter, begins to increase toward maximum value (fsmax). at this time, s-shaped curve appears in fein if the system is normal. fein is converted to fzc signal through fzc comparator. when this fzc signal downcome is detected, f_loopon signal comes to h to allow the loop close and, at this time, fsearch voltage is held. fsmin is set by &hc8[3:0] and fsmax set by &hc8[7:4] respectively. the fsearch voltage decremental speed rate is set up by &hc9[2:0] and the fsearch voltage incremental speed rate set up by &hc9[6:4]. furthermore, inverted-s shaped curve appears on fein while fsearch volt age is decrementing. under this inverted-s shape, it can be selectable whether the loop is turned on or not, by &hc9[7]. if fzc signal is failed to be detected, fsearch voltage increments and decrements smoothly and repeatedly in the range of fsmin to fsmax. it can be discriminated whether fsearch voltag e is incrementing or decrementing, by fsdown internal signal. each signal of f_loopon and fsdown can be read as the internal status. for the detail refer to description of command interface. downloaded from: http:///
222/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 17.3.13.2. focus recovery fsearch =fdout fok fzc fein fsmin fsmax fslo s -curve fsrv f_loopon figure 88. focus recovery operation timing chart this function is intended for focus re-searching in the case of focus failure during playback. if fok signal l level continues for fslo time only, fsearch voltage decrements to the recovery start voltage (fsrv) and thereafter begins to increment toward fsmax. subsequently th e same operation as focus search operation is executed and the loop turns on. in addition, after this focus recovery operation, the tracking goes into gain-up + half-wave brake co ndition to quicken tracking completion. the precondition for resetting gain-up and half-brake is same as that for tr jump. for the detail refer to description of tr jump. further, fslo time is set up by &hca[6:4] and fsrv voltage set up by &hca[3:0]. downloaded from: http:///
223/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 17.3.14. fzc comparator comp fein lim (sens) fzcth / fzct l figure 89. fzc comparator actuation block diagram fzc comparator actuates upon comparison of the fein signal with the threshold value. fzc signal is used for detection of s-shaped focus as descrip tion in focus search. the figure below shows the timing chart (example). fsearch =fdout fsdown fzctl fzcth fein s -curve fzc fzctl fzcth figure 90. fzc comparator operation timing chart the threshold value can be set individually for l h (fzcth) and h l (fzctl). the setting commands used are &hf2[7:4] and [3:0]. also, the zone above s-shaped vc is compared with the setup threshold value when f_search voltage is incrementing (fsdown is l), and the zone below s-shaped vc is compared with the setup threshold value when f_search voltage is decrementing (fsdown is h). downloaded from: http:///
224/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 17.3.15. cd-rw detection and gain setting fsfzc signal is used to detect cd-rw disc. this signal comes to h when fzc is detected even once during focus search, internal signal which returns to l after reset by issue of focus off command. because of its reflectance lower than press disc and cd-r disc, cd-rw disc is held as fsfzc=l, if h-side comparate level is set properly by command &hf2[7:4], whereby present disc can be judged to be cd-rw disc. fsfzc signal can be read from internal status. furthermore, at this time each gain in rf is increased by command &h61[5:4] and it is enable to get optimum gain setting for cd-rw. downloaded from: http:///
225/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 17.3.16. track jump commands for jump in outer peripheral direction commands for jump in inner peripheral direction description &hc400 &hc600 for 1 tr jumping &hc4xx &hc6xx for tr jumping at setup value*2 when setup value is other than 00 &hc5xx &hc7xx sled move on tr at setup value*128 table 17.3.16. commands for jumping and description of each commands 17.3.16.1. tr jump this jump is effected when command &hc400 or &hc600 is issued. issue of command busy tr1w tha thb trbt tdout wq cout tjgup figure 91. tr jump (by issue of &hc400) timing chart after issue of the command, busy signal comes to l. at this time, the tracking filter is put in dc hold condition and the data added acceleration pulse and lpf output is output from tdout terminal. the acceleration pulse height (tha) is set up using command &hfd[7:4]. the acceleration pulse is output continually until cout signal rises after cout signal had held l for a time longer than the blind time (trbt). trbt is set up using command &hcc[7:4]. deceleration pulse is output from tdout terminal for the time of (acceleration pulse output time) tr1w, commencing from the time point when the acceleration pulse output ended. the deceleration pulse height (thb) is set up by command &hfd[3:0] and tr1w set up by command &hcb[7:6]. upon completion of the jump pulse output, busy signal comes to h, showing tr jump ended. and the tracking filter goes into gain-up + half-wave brake condition. return of the filter to t he usual condition from this condition is effected when wq has come to h. for the gain-up mode and half-wave brake mode, refer to the description of these modes given later separately. also, when jumped in inverted direction, tdout output positive and negative values are inverted. downloaded from: http:///
226/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 17.3.16.2. the signal used for track number counting at multi tr jump/sled move cout cout cout tzc tzc tr count figure 92. relation of the signal used for track number counting at multi tr jump at multi tr jump and sled move, either cout or tzc signal is selected for the signal used for tr number counting by the period of signal. for this, cout signal is used for tr number counting signal when the period is slow and when the period is fast, tzc signal is used. it is enable to set the period to change the signal using for tr number counting by command &hcb[3:0]. downloaded from: http:///
227/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 17.3.16.3. multi tr jump (1) this multiple track jump is effected when the command is &hcb[5]=0, after issue of command &hc4xx or &hc6xx. (xx: other than 0) issue of command busy sh tha thb trlst trot 3 2 1 tr count start trbt tdout wq cout sdout tjgup figure 93. multi tr jump (1) (by issue of &c403) timing chart after issue of the command, busy signal comes to l. at this time, the tracking filter is put in dc hold condition and the data added acceleration pulse and lpf output data is output from tdout terminal. the acceleration pulse height (tha) is set up using command &hfd[7:4]. also, output of acceleration pulse from sdout terminal begins simultaneously, too. sled pulse height (sh) set up using command &hfe[7:4]. tr number counting begins with rise of cout signal after cout signal had held l for the time longer than blind time (trbt). trbt is set up by command &hcc[7:4]. either cout or tzc signal is selectable by command &hcb[4], as the signal useing for tr number counting. when cout signal is selected, by co mmand &hcb[3:0], either cout or tzc signal is changed for the signal using for tr number counting by the period of tr number counting. the acceleration pulse from tdout terminal is output continually until tr number counted value reaches the setup value. on the other hand, output of deceleration pulse from tdout terminal begins with end of the acceleration pulse output and is continued until cout signal downcome after cout signal had held h for the time longer than overflow time (trot). this deceleration pulse height (thb) is set up by command &hfd[3:0] and trot is set up by command &hcc[3:0]. upon completion of the jump pulse output from tdout terminal, the tracking filter goes into gain-up + half-wave brake condition. return of the filter to the usual condition from th is condition is effected when wq has come to h. for the gain-up mode and half-wave brake mode, refer to the description of these modes given later separately. acceleration pulse output from sdout terminal is continued excessively for trlst time after completion of pulse output from tdout terminal. this is to enable adequate sled feed in executing tr jumping because usually the sensitivity of sled motor sensor is lower than that of tr actuator sensor. after completion of acceleration pulse output from sdout terminal, busy signal comes to h, showing that tr jump ended. trlst time is set up by command &hcd[6:0]. also, when jumped in inverted direction, tdout and sdout output positive and negative values are inverted. downloaded from: http:///
228/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 17.3.16.4. multi track jump (2) this multiple track jump is effected when the command is &hcb[5]=1, after issue of command &hc4xx or &hc6xx. (xx: other than 0) issue of command busy sh tha thb trls t trot tdout wq cout sdout tjgup trot figure 94. multi tr jump (2) (by issue of &hc410) timing chart under this mode, tr jump similar to jumping by feed of &hc408 in multi tr jump (1) mode is continued up to the cycles set up by &hc4[7:3]. however, the precondition for discontinuing deceleration pulse output from tdout terminal at the jump go-on point is not cout signal downcome but the moment when h-section of cout signal exceeded the blind time. busy signal comes to h when sled acceleration pulse output has ended. furthermore, in the case of this jump mode, it is prohibited to send such a command (ex. &hc403) that &hc4[7:4] comes to 0, except 1 tr jump command. also, when jumped in inverted direction, tdout and sdout output positive and negative values are inverted. downloaded from: http:///
229/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 17.3.16.5. sled move mode effected when command &hc5xx or &hc7xx is issued. issue of command b usy sh w q cout sdout tjgup tr count start trbt figure 95. sled move (by issue of &hc5xx) timing chart after issue of the command, busy signal comes to l and acceleration pulse is output from tdout terminal. the sled pulse height (sh) is set up using command &hfe[7:4]. at this time, vc is output from tdout terminal. tr number counting begins with rise of cout signal after cout signal had held l for the time longer than blind time (trbt). trbt is set up by command &hcc[7:4]. either cout or tzc signal is selectable by command &hcb[3:0], as the signal used for tr number counting. the acceleration pulse is output continually until tr number counted value reaches the setup value*128. upon completion of the jump pulse output, the tracking filter stops vc output and goes into gain-up + half-wave brake condition. return of the filter to the usual condition from th is condition is effected when wq has come to h. for the gain-up mode and half-wave brake mode, refer to the description of these modes given later separately. upon completion of acceleration pulse output from sdout terminal, busy signal comes to h, showing that sled move has completed. also, when the sled moves in inverted direction, sdout output positive and negative values are inverted. downloaded from: http:///
230/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 17.3.17. tracking half-wave brake mode the figure below shows the brake timing chart in tr half-brake mode in the case of jump in outward direction. tein cout tdout half wave brake tjgup figure 96. brake timing chart in half-wave brake mode after tr jump pulse output ended, the pickup continues to move by its inertia. it is really difficult to stop the inertia movem ent, which then cause tr guiding into tr servo loop to get worse. at this time, if the tr half-wave brake mode turns on, the cout signal acts to turn on tr filter loop when the signal is in l section and acts to turn off the same loop when the signa l is in h section. this means that braking is applied to jump di rectional movement of the pickup, whereby tr servo can be reset earlier. this mode is automatically turned on after tr jump and focus recovery using command &hcf[4], and reset when wq=h. for delaying more the reset timing, reset this mode manually using command &hce[7]. further, when jumped in reverse directi on, tein waveform and tdout output positiv e and negative values are inverted and tr loop turns on only when braking is applied in jumping direction. 17.3.18. tracking gain-up mode this is the mode used to stabilize tr earlie r, where it is unstable. for that, tr se rvol filter through (medium area) and bpf (high area) gains are increased by tgup. tgup is set up using command &hec[5:4]. this mode turns on simultaneously with tr half-wave brake mode after tr jump and when focus recovery which is selected by command &hcf[4] is executed and the mode is reset when wq=h. for delaying more the reset timing, however, reset this mode manually using command &hce[7]. also, on occasion this mode turns on independently. it does so under anti-shock mode. for the anti-shock mode detail, refer to description of ats comparator. downloaded from: http:///
231/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 17.3.19. sled intermittent feed figure 97. sled intermittent feed timing chart this function is intended to control on/off of output to sdout terminal, based on the preset threshold value. usually an insensible zone exists in the sled motor. therefore, useless ener gy is consumed while the output is kept on in the insensible zone. so, this function is turned on to prevent useless power consumption. comparate level is set up individually for on-side sth and off-side stl. sth is set up using command &hf0[6:0] and stl set up using command &hf1[6:0]. furthermore, validate/invalidate of this function can be selected using command &hcf[7]. downloaded from: http:///
232/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 17.3.20. auto adjustment and measurement this is the sequence to be followed after command &hd0xx was sent. when the measurement has completed correctly, the measured result is read using command &hde. as to how to read, refer to description of command interface. the table below lists respective commands and the measuring conditions, together with the commands used for adjustment of the respective values. command for measurement measuring items measuring conditions command for adjustment &hd01x sdout offset befo re fo servo on &h91xx &hd02x fdout offset before fo servo on &h92xx &hd03x tdout offset before fo servo on &h93xx &hd04x ac offset before fo servo on &h640x &h94xx &hd05x bd offset before fo servo on &h650x &h95xx &hd06x e offset before fo servo on &h660x &h96xx &hd07x f offset before fo servo on &h670x &h97xx &hd08x focus balance (in case of using max/min) fo servo off &h98xx (in case of using rfrp) fo servo on, tr servo on &hd09x tracking balance fo servo on, tr servo off &h99xx &hd0ax focus gain fo servo on, tr servo on &h9axx &hd0bx tracking gain fo servo on, tr servo on &h9bxx &hd0cx rf offset (at setting initial value) fo servo off &h9cxx (at playback) fo servo on, tr servo on &hd0cx rf gain fo servo on, tr servo on &h9dxx &hd0ex vco offset before fo servo on &h9exx &hd0ex vco gain before fo servo on &h9fxx table 17.3.20. auto adjustment command and adjustment command design is so made that the larger measured data can be got correspondingly by setting up the adjustment commands at larger values. the measuring procedure is described in detail hereunder. downloaded from: http:///
233/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 17.3.20.1. measurement of ac/bd/e/f offset these measurement are executed when either one of commands &hd04x to &hd07x is issued. ac/bd/e/f offset can be canceled by setting each offset value by applicable command. adc fc = 194hz fc = 194hz output (read by &hde) lpf digital offset2 lpf analo g in analog offset digital offset1 figure 98. block diagtam relating to ac/bd/e/f offset measurement when the command to measure offset is issued, adc selects an input signal and offset is added to output value. by analog offset, offset adjustment is executed ro ughly not to over the d-range of adc. digital offset1 is added for making adc output to vc, and set up in proportion to the initial value of ana log output. digital offset2 is for close offset adjustment. commands for measurement analog offset digital offset1 digital offset2 ac offset &hd04x &h64[2:0] &hf6[6:4] &h94[7:0] bd offset &hd05x &h65[2:0] &hf6[6:4] &h95[7:0] e offset &hd06x &h66[2:0] &hf6[2:0] &h96[7:0] f offset &hd07x &h67[2:0] &hf6[2:0] &h97[7:0] table 17.3.20.1. commands for adjustment ac/bd/e/f offset wait for latch (about 11us) issue of command l busy end of measurement waito sens (about 17us) figure 99. timing chart relating to ac/bd/e/f offset measurement busy signal comes to l in about 17us after issue of the command. adc output passes through primary lpf 2 stages after offset added. lpf output is latched at the time point when waito time has passed. thereafter, the busy signal comes to h, showing the measurement ended. read the result using command &hde. waito time is the waiting time until measurement stabilizes, which is set up using command &hd2[7:4]. further, sens=l remains unchanged in measuring ac/bd/e/f offset. downloaded from: http:///
234/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 17.3.20.2. measurement of fd/td offset these measurements are executed when the command either &hd02x or &hd03x is issued. fd/td offset can be canceled by setting each offset value by applicable command. ad c fc = 194h z fc = 194h z output (read by &hde) lpf fd offset/ td offse t ac/ e bd/ f ad c lps lpf lpf bpf ft g fg/tg figure 100. block diagram relating to fd/td offset measurement issue of command l busy end of measurement waito sens (about 17us) wait for latch (about 11us) figure 101. timing chart relating to fd/td offset measurement commands for measurement fd offset/ td offset fd offset &hd02x &h92[7:0] td offset &hd03x &h93[7:0] table 17.3.20.2. command for adjustment fd/td offset busy signal comes to l in about 17us after issue of the command and measurement is started. at this time, if command is &hd02x, input signals to adc come to ac and bd signal and if command is &hd03x, come to e and f signal. adc output passes through lps and lpf of servo filter and primary lpf 2 stages after offset added. lpf output is latched at the time point when waito time has passed. thereafter, the busy signal comes to h, showing the measurement ended. read the result using command &hde. waito time is the waiting time until measurement stabilizes, which is set up using command &hd2[7:4]. further, sens=l remains unchanged in measuring fd/td offset. downloaded from: http:///
235/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 17.3.20.3. measurement of sd offset this measurement is excuted when command &hd01x is issued. sd offset can be canceled by setting offset value by applicable command. sd_offset sg s-lps fc = 194hz fc = 194h z lpf lpf output (read by &hde) td_lpf_out figure 102. block diagram rerating to sd offset measurement wait for latch (about 11us) issue of command l busy end of measuremen t wait o sens (about 17us) figure 103. timing chart relating to sd offset measurement busy signal comes to l in about 17us after issue of the command and measurement is started. in the case of using digital sled filter, the input signal comes to lpf output signal of tracking filter and it passes through sled filter after offset adde d.after the signal passed sled filter, the output signal passes through primary lpf 2 stages. and lpf output is latched at the time point when waito time has passed. thereafter, the busy signal comes to h, showing the measurement ended. read the result using command &hde. sd_offset is adjustable by the command &h91[7:0]. further, sens=l remains unchanged in measuring sd offset. downloaded from: http:///
236/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 17.3.20.4. measurement of tracking balance (method 1) at command &hd4[1] is l, amplitude center of te signal is measured by issue of command &hd09x. it is possible to cancel deviation from vc by combining this function with the tracking balance adjust function. comp fc = 194hz fc = 194hz e f tbco lpf tedlp ted eg lpf teof fg eof fof figure 104. tracking balance measuring block diagram (method 1) wait for latch (about 11us) issue of command l busy end of measurement condition check wai t o sens (about 17us) figure 105. tracking balance measuring timing chart (method 1) busy signal comes to l in about 17us after issue of the command, and measurement is started. at this time offset is added to each of e and f signals from adc output, and by subtract these signals, te signal is generated. original signal (ted) is compared with tedlp signal through lpf and consequently tbco signal is ready for output. when measuring tracking balance, turn off tracking servo loop by command &hc1[5:4]=0. and according to cases, use sled move in combination with this function. first of all this function is put in wait condition for waito time until e and f signals stabilizes, and thereafter discriminat ion of the preconditions for measurement ok is started. the m easurement is judged as ok when tbco has continued by tbn cycles within the cycle range of tbmin to tbmax. upon judgement of measurement ok, tedlp value at that time is latched as the result. thereafter, busy signal comes to h, showing completion of the measurement. read the measured result using command &hde. at this time, if sens=l, it shows that the measurement was made correctly. if sens=h, it shows that ng condition has took place during measurement, t hat is, showing that either fok came to l (fok=l) during measurement or measurement ok conditions failed to be met for 65ms (time-out). in the case of sens=l, read the result by command &hde. set up waito by command &hd2[7:4], tbmin by command &hd3[7:4], tbmax by command &hd3[3:0], and t bn by command &hd4[7:4]. downloaded from: http:///
237/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 (method 2) at commancd &hd4[1] is h, max/min values of te signal are measured by issue of command &hd09x. by this method, with adjustment the balance of upper and lower sides of tracking error signal, it is also possible to cancel deviation from vc by combining this function with the tracking balance adjust function. e f eg teof fg e-f e-f ( max ) e-f ( min ) eof fof figure 106. tracking balance measuring block diagram (method 2) issue of command l b usy end of measurement waito sen s (about 17us) wait for latch wai t _ tb figure 107. tracking balance measuring timing chart (method 2) busy signal comes to l in about 17us after issue of the command, and measurement is started. at this time offset is added to each of e and f signals from adc output, and by these signals, e-f signal is generated. the reading signal is selectable by command &hd5[1:0], max or min value of e-f signal can be selected. when measuring tracking balance, turn off tracking servo loop by command &hc1[5:4]=0. first of all this function is put in wait condition for waito time until e and f signals stabilizes, and thereafter max and min values are measured during wait_tb time. these values at t hat time are latched as the result.thereafter, busy signal comes to h, showing completion of the measurement. read the measured result using command &hde. at this time, if sens=l, it shows that the measurement was made correctly. if sens=h, it shows that ng condition has took place during measurement. ng condition is that fok came to l (fok=l) during measurement. in the case of sens=l, read the result by command &hde. set up waito by command &hd2[7:4], and wait_tb by command &hd2[3:0]. downloaded from: http:///
238/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 17.3.20.5. measurement of focus balance (method 1) at command &hd4[1] is l, rfrp deviation from its maximum amplitude point is measured by issue of command &hd08x. it is possible to get rf amplitude maximum point by combining this function with the focus balance adjusts function. comp fc = 194hz fc = 194hz rfrp fbco lpf rfrpdlp rfrpd lpf figure 108. focus balance measuring block diagram (method 1) issue of command busy end of measurement count count u p / down *16 oscf oscg waito fbco sens wait for latch (about 11us) (about 17us) gairan figure 109. focus balance measuring timing chart (method 1) busy signal comes to l in about 17us after issue of the command and at the same time measuring is started. at this time, original signal (rfrpd) is compared with rfrpdlp signal having passed through lpf and consequently fbco is ready for output. on the other hand, fo servo loop keeps as on, but distur bance signal is as added automatically. it is possible to set up the height of this disturbance by command &hed[5:0] and frequency thereof by command &hed[7:6] respectively. at first, this measurement function waits for waito time until rfrp stabilizes. thereafter, this function starts measuring with initial rise of the disturbance signal. this measurement is ef fected by the counter operation. when disturbance is in positive section, the section of fbco=h is counted up. also, the sect ion of fbco=h is counted down when disturbance is in the negative section. the measurement ends when such counter operation was repeated 16 times and the mean value of counter values is latched as the measured result. thereafter, busy signal comes to h, showing that the measurement ended. at this time, if sens=l, it shows that the measurement was made correctly. if sens=h, it shows that setup ng condition took place during measurement. as measurement ng condition, any one of lock=l or gfs88=l or nothing can be selected by command &hd4[3:2]. in the case of sens=l, read the result by command &hde. downloaded from: http:///
239/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 figure 110. focus balance measuring principle chart (method 1) when disturbance signal is added to fdout, rfrp response differs depending on which is the focal point of the focus, of a to e points. herein, rfrp response characteristic is shown in graphs assuming the case of no phase deviation. as seen from the above graph, rfrp phase against disturbance in the case of focal point-a is reverse to that in the case of focal point-e. this focus balance measuring function uses fbco which is the comparative data of rfrp lpf component (=mean value) and rfrp. hence, as prescribed it is possible to discriminate dev iation direction of the focal point by comparing the time of fbco=h under positive disturbance with the time of fbco=h under negative disturbance. the disturbance frequency is set to several hundred hz because the focus sounds at high db if the frequency comes to nearly 1khz. downloaded from: http:///
240/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 (method 2) at command &hd4[1] is h, max/min values of s-shaped curve at focus search are measured by issue of command &hd08x. by this method, it is excuted to adjustment the blance of upper and lower sides of s-shaped curve by combining with the focus balance adjust function. ac bd acg feof bdg a c -bd ac-bd ( max ) ac-bd ( min ) acof bdof figure 111. focus balance measuring block diagram (method 2) issue of command l b usy end of measurement sens (about 17us) f dout fe(ac-bd) figure 112. focus balance measuring timing chart (method 2) busy signal comes to l in about 17us after issue of the command, and measurement is started. at this time offset is added to each of ac and bd signals from adc output, and by these signals, ac-bd signal is generated. the reading signal is selectable by command &hd5[1:0], max or min value of ac-bd signal can be selected. after measurement started, focus search is executed and in the meantime, max/min values of ac-bd signal are measured. thereafter, busy signal comes to h, showing completion of the measurement. read the measured result using command &hde. further, sens=l remains unchanged in measuring fd/td offset. downloaded from: http:///
241/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 17.3.20.6. measurement of tracking gain and focus gain this measuring function is effected by issue of either &h d0ax or &hd0bx, intended to measure phase difference between disturbance signal applied to the servo loop and tein/fein signal. optimum gain can be set up by adjusting both of tracking gain and focus gain based on the measured result. comp 0 bpf tgco / fgco lpf te / fe tg / fg tg / fg hpf gairan oscg figure 113. tracking gain/focus gain measuring block diagram the block enclosed with dotted line covers the internal portions of tr servo filter /fo servo filter. issue of command busy end of measuremen t count u p *16 coun t oscf oscg waito fgco / tgco sens wait for latch (about 11us) (about 17us) gairan figure 114. tracking gain/focus gain measuring timing chart busy signal comes to l in about 17us after issue of the command and at the same time measuring is started. at this time, the servo loop keeps on, but disturbance signal is as added automatically. in addition, the signal having passed through bpf is compared with 0 and tgco/fgco is ready for output, as illu strated above. it is possible to set up the height of this disturbance by command &hed[5:0] and frequency thereof by command &hed[7:6] respectively. furthermore, at this time the center frequency of bpf is changed according to the setup disturbance frequency. at first, this measurement function waits for waito time until te/fe stabilizes. thereafter, this function starts measuring wit h initial downcome of the disturbance signal. this measurement is effected by the counter operation. the counter counts up for the time from change-over point from positive disturbanc e to negative disturbance until rise of tgco/fgco. the measurement ends when this cyclic operation is repeated 16 times and the mean value of the counter counted values is latched as the measured result. thereafter, busy signal comes to h, showing that the measurement ended. at this time, if sens=l, it shows that the measurement was made correctly. if sens=h, it shows that setup ng condition took place during measurement. as measurement ng condition, any of lock=l or gfs88=l or nothing can be selected by command &hd4[3:2]. in the case of sens=l, read the result by command &hde. downloaded from: http:///
242/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 (a)gain <<0db gairan+te / fe P bpf output te / fe gairan count(a) < count(b) < count(c) (b)gain =0db (c)gain >>0db count(a) count(c) count(b) figure 115. tracking gain/focus gain measuring principle chart the object of gain adjustment is to align the servo loop gain under 1khz to 0db. in the above chart, disturbance is represented by dotted li ne, te/fe represented by broken line, and bpf input signal represented by solid line. the peak frequency of bpf can be al igned to disturbance and, therefore, bpf output could be considered to be nearly same as bpf input. comparing the case of higher gain (than 0db) with the case of lower gain (than 0db), the result is as shown in the above chart. however, in (c) graph the vertical axis is compressed to express disturbance level so it gets smaller. the counter counts from zero-cross point of disturbance downcome until zero-cross point of bpf output rise. comparing this cycle count time, the result is as follows; count(a) 243/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 17.3.20.7. about rf amplitude measurement and the adjustment peak and bottom value of the amplitude of rf (eqo) signal are measured by excute out command &hd0cx. dc level and amplitude of rf signal can be adjusted by combining it with rf offset adjustment command &h9c0x and rf gain adjustment command &h9dxx. and, it can get the most suitable rf signal from the viewpoint of dc by combining it with fok comparate level adjustment command &haa[3:0]. (for the detail, refer to rf signal generator) issue of command b usy end of measurement wai t waito sen s (about 17us) rf fin g e r figure 116. rf amplitude measuring timing chart busy signal comes to l in about 17us after issue of the command, and measurement is started. the reading signal is selectable by command &hd5[1:0], max and min value can be selected. first of all this function is put in wait condition for waito time until rf offset signal stabilizes, and thereafter max and mi n values are measured during wait time. these values measured at that time are latched as the result. thereafter; busy signal comes to h, showing completion of the measurement. read the measured result using command &hde. at this time, if sens=l, it shows that the measurement was made correctly. if sens=h, it shows that ng condition has took place during measurement, that is, showing that either measurement ng conditions selected by command &hd4[3:2] are met or fok came to l during measurement. in the case of sens=l, read the result by command &hde. set up waito by command &hd2[7:4], and wait command &hd2[3:0] with full time to pass through the finger and etc.. and, the case of measuring rf signal before focus servo turned on, make command &hd4[1] to h. downloaded from: http:///
244/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 17.3.20.8. measurement of vco frequency of vco output signal is measured by issued command &hd0ex. at this time, vco input voltage is selectable and it is possible to measure the frequency of vco output signal at each case. by combining this result with the vco offset/gain adjustment function, optimum offset/gain can be set up. output ( read b y &hde ) vco div counter figure 117. vco measuring block diagram issue of command l busy end of measurement waito sens (about 17us) wait for latch (about 11us) figure 118. vco measuring timing chart busy signal comes to l in about 17us after issue of the command and at the same time measuring is started. at command &h8a[6] is h, vco input voltage can be set up by changing command &h8bxx. the frequency of vco output is measured by a counter after divided and the frequency is latchd as the result. thereafter, busy signal comes to h, showing that the measurement ended. so read the result by command &hde. waito time is a wait time set up by command &hd2[7:4] for vco output is stabilized and the count value is latched. the division ratio of vco output signal is possible to change by command &h50[7:6]. and when measuring, set up pll measuring mode as for vco measuring by command &h82[5:4]=h3. further, sens=l remains unchanged in measuring vco. 17.3.20.9. the case of sending continuously automatic adjustment and measurement commands it is prohibited to send continuously different commands for automatic adjustment and measurement while one automatic adjustment and measurement command is on. in such a case, send &hd00x without fail at once, and thereafter start new measurement. on the other hand, where same measurement is repeated, wa it time for each measurement is omitted and, hence, quick remeasurement is available. downloaded from: http:///
245/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 17.3.21. detection of defec t disc and countermeasures on occasion flaw exists on disc to be reproduced. it is not allowed that the performance of each servo is disordered by disc flaw. to avoid such a phenomenon, disc surface must be detected and appropriate countermeasure be undertaken against it. mainly 4 different flaws defined hereunder could exist on disc for evaluation of playability. ac tual disc flaw may be considere d to be a composite of these 4 different flaws. 17.3.21.1. black dot this is a dot which is printed in ink on the read surface of disc, simulated from foreign matter adhered to disc and resin blac k dot in disc. reflection light from disc is quite eliminated at black point. defect signal generated by rf is used for detection of such black dot. this signal is a signal which comes to h when eye level is low. in the case of defect=h, countermeasure for the focus and that for tacking are set up using command &hd6[7:6] and &hd6[3:2] respectively and each of them can be selected from three systems of no countermeasure, hold, and gain down. 17.3.21.2. interruption this is a disc flaw which was simulated from pit interruption on flawed aluminum deposition surface. at this interruption spot, brightness-darkness difference in reflection light from disc depending on pitted surface is perfectly eliminated and, as a resu lt, eye signal comes to h. hence, the prescribed de fect signal is kept as l (not detected). new_defect signal is used for detection of this disc interruption. in the case of new_defect=h, countermeasure for the focus and that for tracking are set up using command &hd6[5:4] and &hd6[1:0] respectively and each of them can be selected from three systems of no countermeasure, hold, and gain down. 17.3.21.3. fingerprint fingerprint means a fingerprint-like pattern, which was printed on disc read surface. such a disc flaw is not detected and also no countermeasure is taken for it. 17.3.21.4. scratch this scratch means a frictional flaw on disc read surface. some of frictional flaws is called red band, which is flaw simulated from scratch. in the case of this disc flaw, it is not specially detected and no special countermeasure is taken for it, but defect and new_defect could be detected though depending on amplitude level of rf. 17.3.21.5. pll action in passing through flawed spot of disc when defect and new_defect are h, the pll circuit perfo rms hold operation and prevents the frequency of plck deviating at the time of passing through flawed spot of a disk downloaded from: http:///
246/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 17.3.22. pre-servo amp 17.3.22.1. rf signal generator _[] _[] _[] _[] _[] _ _[] _[] __ __ _ _ _[] figure 119. rf signal generator downloaded from: http:///
247/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 this rf signal generator gets a+b+c+d from signals sent from the pickup and finally generates asymmetrically-corrected efm signals. where reproduced disc is cd-r/w, the gain can be increased by +9.5db or +14db by setting cdrw_sel to 1h or 2h as shown in table 17.3.22.1.0. respectively. acbd_cap is capacitor for phase compensation. it is possible to set up as shown in table 17.3.22.1.2 asymmetrically-corrected efm signal is output from efm. asy terminal is provided with a capacitor to get asymmetrically-corrected comparator slice level signal. the equalizer (rfeq) is structured with equi-ripple filter. group delay is constant independ to boost level. the equalizer set as shown in tables table 17.3.22.1 ! ? ? .3 C table 17.3.22.1.5 the shift amount of base level of rf output (eqo) can be set at 16 steps by rf_offset[3:0].(table 17.3.22.1.6) rf gain can be set at ? 6db by rf_gain[4:0].please set the command to make eqo output voltage between 1.0vp-p and 1.2vp-p when eqogca_id =4h.(table17. 3.22.1.1) by being set as pwroff_ih=1, the power down m ode to minimize consumption current is selected. cdrw_sel[1:0] ac/bd gain e/f gain 0h 0db 0.0db 1h 9.5db 9.5db 2h 14.0db 9.5db table17.3.22.1.0. cdrw_sel setting values by command &h61[5:4] gain (db) g=20log[100/{(31-&h9d[4:0]) ? 5+50}] rf_gain[4:0] rf gain 01h -6.0db 15h 0.0db 1fh 6.0db table17.3.22.1.1. rf_gain setting values by command &h9d[4:0] acbd_cap_ sel acbd_cap 0h 0.25 pf 1h 0.125 pf table17.3.22.1.2. acbd_capa_sel setting values by command &h60[1] h62[5:4] apcisel_ih[3:0] f 0 speed 0h 1h 0.72mhz x1 1h 2h 1.45mhz x2 2h 4h 2.90mhz x3 to x4 3h 8h --- through table17.3.22.1.3. rf_capa_sel setting values by command &h62[5:4] downloaded from: http:///
248/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 h62[3:2] eqogca_id[2:0] rfeq total gain 0h 1h 6db 1h 2h 9db 2h 4h 12db 3h 8h --- table 17.3.22.1.4. eqogca_id setti ng values by command &h62[3:2] rfbst_id [1:0] boost rfbst_id [1:0] boost 0h 2db 2h 6db 1h 4db 3h 8db table 17.3.22.1.5. rfbst_id setting values by command &h62[1:0] rf_offset [3:0] eqo basic level rf_offset [3:0] eqo basic level rf_offset [3:0] eqo basic level rf_offset [3:0] eqo basic level 00h vc-2.00v 04h vc-1.20 08h vc-0.40v 0ch vc+0.40v 01h vc-1.80v 05h vc-1.00v 09h vc-0.20v 0dh vc+0.60v 02h vc-1.60v 06h vc-0.80v 0ah vc 0eh vc+0.80v 03h vc-1.40v 07h vc-0.60v 0bh vc+0.20v 0fh vc+1.00v table 17.3.22.1.6. rf_offset setting values by command not(&h9c[3:0]) downloaded from: http:///
249/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 17.3.22.2. fe/te signal generator _[] _[] _[] _[] figure 120. fe signal generator _ _[] _ _[] figure 121. te signal generator downloaded from: http:///
250/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 at fe signal generator, it gets a+c, b+d signals being sent from the pickup and generates focus error signals a+b, b+d. at te signal generator, it gets e, f signals being sent from the pickup and generates tracking error signals e, f. thereafter, the focus signals and tracking signals are s ent to adc and after adc, (a+c)-(b+d) signal and e-f signal are gen erated at digital block. be concerned about each of input a+c, b+d, e, f, offset adjustment can be made individually by setting ac_offset, bd_offset, e_offset, f_offset as shown in table 17.3.22.2.0 and table 17.3.22.2.1. where reproduced disc is cd-r/w, the fe gain can be increased by +9.5db or +14db and te gain can be increased by +9.5db by setting cdrw_sel to 1h or 2h as shown in table 17.3.22.2 ! ? ? .0 respectively. moreover, by connecting resistances and capacitors to ac_gain terminal and bd_gain terminal of fe signal generator and to e, f input terminals of te signal generator, adjustment of gain and cut-off frequency can be carried out by these co nstants. te signal generator can be change gain by setting fe_gain[3:0] as shown in table 17.3.22.2.2 by being set as pwroff_ih=1, the power down m ode to minimize consumption current is selected. ac_offset[2:0] bd_offset[2:0] dc level ac_offset[2:0] bd_offset[2:0] dc level 0h vc 4h vc-0.88v 1h vc-0.22v 5h vc-1.10v 2h vc-0.44v 6h vc-1.32v 3h vc-0.66v 7h vc-1.54v table 17.3.22.2.0. ac_offset and bd_offset setup values by command &h64[2:0], &h65[2:0] (vcc=3.0v) e_offset[2:0] f_offset[2:0] dc level e_offset[2:0] f_offset[2:0] dc level 0h vc+1.54 4h vc+0.66v 1h vc+1.32v 5h vc+0.44v 2h vc+1.10v 6h vc+0.22v 3h vc+0.88v 7h vc table 17.3.22.2.1. e_offset and f_offset setup values by command &h66[2:0], &h67[2:0] (vcc=3.0v) fe_gain [3:0] fe gain[db] fe_gain [3:0] fe gain[db] fe_gain [3:0] fe gain[db] fe_gain [3:0] fe gain[db] 00h 0.37 04h 2.03 08h 4.08 0ch 6.77 01h 0.75 05h 2.50 09h 4.68 0dh 7.60 02h 1.16 06h 3.00 0ah 5.32 0eh 8.32 03h 1.58 07h 3.50 0bh 6.00 0fh 9.54 table 17.3.22.2.2. fe_gain setup values by command &h68[3:0] (vcc=3.0v) downloaded from: http:///
251/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 apc circuit _ _ _ _[] _ _ _ figure 122. apc circuit laser power is automatically controlled by feeding back the detected power with signal from photo detector. by setting command &h60[4] to h, laser can be turned on by setting ldon_ih to 1. the reference level can be set by apc_id[3:0] and table 25.3.0 is showing the setup values. by setting apc_inv_sw(command &h60[0]) to h, it invert basic level(vcc level). power down mode to minimize consumption current is selected by setting pwroff_ih to h. apc_id [3:0] level apc_id [3:0] level apc_id [3:0] level apc_id [3:0] level 0h 145mv 4h 165mv 8h 185mv ch 205mv 1h 150mv 5h 170mv 9h 190mv dh 210mv 2h 155mv 6h 175mv ah 195mv eh 215mv 3h 160mv 7h 180mv bh 200mv fh 220mv table 17.3.22.2.3. apc_id setup value by command &h61[3:0] downloaded from: http:///
252/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 17.3.22.3. det circuit comparator sequencer 6bit dac (rf) figure 123. det circuit __ [] figure 124. det circuit operation principle this detection circuit is to detect peak and bottom points of rf signal and by each long signal and short signal of those, fok signal, mirror signal, defect signal and rf ripple signal are generated. detection of peak and bottom points is executed by referring to the comparison result of rf signal and 6bitdac output voltage. thereafter, the result is sent to sequencer and ne xt input pattern to dac is decided. the input pattern to dac obtained by these ways becomes peak and bottom signals. wh ich between peak and bottom is detected, and which signal between a long signal and a short signal is detected are changed by sequence. also the width of increase and decrease of dac output value can be set by dacin_plus_sel[1:0] (command &ha8[5:4]) power down mode to minimize consumption current is selected by setting pwroff_ih to 1. 17.3.22.3.1. fok signal generator bottom_long peak_short fok_ref[3:0] fok peak_long fok_ref[3:0] fok bottom_long peak_short peak_long min. level of dac_det command &haa[4]=h (amplitude judgement) command &haa[4]=l (peak_long level judgement) figure 125. fok circuit operation principle generation of fok signal is executed using peak_long signal, peak_short signal and bottom_long signal. when focus is failed, peal_long signal increases. then if peak_long signal becomes smaller than fok_ref[3:0] level, fok signal turnes to l. and when focus is recovered, peak_short signal becomes larger, and when peak_short signal becomes larger than fok_ref[3:0] level, fok turns to h. the base level used for judgement of the size of peak signal is selectable by command &haa[4]. in the case of command &haa[4]=h, the base level is bottom_long signal and fok is judged by the amplitude of peak signal and bottom signal. in the case of command &haa[4]=l, the base level is min. level of dac in det circuit and fok is judged by the value of peak_long to that level. moreover, the value of fok_ref[3:0] is possible to set by command &haa[3:0]. downloaded from: http:///
253/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 17.3.22.3.2. defect signal generator bottom_long peak_short def_ref_l[3:0] defect def_ref[3:0] def_hold[2:0] peak_long figure 126. defect circuit operation primciple generation of defect signal is executed using peak_long signal, peak_short signal and bottom_long signal. if flaws are in a disk, when passing through that, a peak s hort signal decreases. and if the difference between peak_long signal and peak_short signal comes to larger than def_ref[3:0] level, defect signal turns to h. then if peak_short signal does not recover while def_hold[2:0] time, defect signal holds h as a flaw is detected. thereafter, when coming off from the flaw, peak_short signal recovers and increases. and the difference between peak_short signal and bottom_long signal becomes larger than def_ref_1[3:0] level, defect signal turns to l. it is possible to set def_ref[3:0] and def_ref_l[3:0] by commands &ha9[7:4] and &ha9[3:0] each other. it is possible to set def_hold[2:0] by commands &hab[2:0]. 17.3.22.3.3. mirror signal generator bottom_long bottom_short mirror mirror_ref [3:0] peak_long figure 127. mirror circuit operation principle generation of mirror signal is excuted using peak_lon g signal, bottom_long signal and bottom_short signal. when passing the mirror side, bottom_short signal increases because the reflection factor becomes higher at that section. then when bottom_short signal exceeds the threshold level of mirror, mirror signal turns h as detected mirror side. the threshold level of mirror is set by carrying out the multiplication of mirror_ref[3:0]/16 to the value which is the result of subtraction of a peak long signal and a bottom long signal. mirror_ref[3:0] is set by command &ha8[3:0]. 17.3.22.4. rfrp signal generator bottom_short peak_short rfrp figure 128. rfrp circuit operation principle the rfrp signal is generated by subtraction of peak_short signal and bottom_short signal and used at focus bias adjustment. for details, refer to the item of focus balance adjustment. downloaded from: http:///
254/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 17.3.22.5. bias voltage generation circuit chip internal external circuit vbias pwdbi 50k 50k op1 figure 129. bias voltage generation circuit this circuit generates the bias voltage v dd /2. this block differs from other blocks, it becomes power down mode to minimize consumption current by setting command &h40[6] pwdbi to1. for this, in case wanting to stabilize bias voltage level early when returning the power mode from power down mode of command&h40[7] pwdrf= 1 to normal oper ation mode, or the case wanting to actuate other ic components which need bias voltage even under powe r down mode, the bias voltage unit generates v dd /2 by setting to pwdbi=0. ? precautions connect pass-control filter of about 10uf to vbias terminal without fail. downloaded from: http:///
255/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 17.3.23. yflag generator yflag is generated by comparision with counter value and threshold (h80). this counter count up when counter enable signal is h and rf ck signal upcome is detect and c2fx signal is h, count down when counter enable signal is h and rfck signal upcome is detect and c2fx signal is l. the setting of this generator set up by command &h47[7:0].the upstep of this counter set up by command &h48[7: 0]. the downstep of this counter set up by command &h49[7:0]. figure 130. yflag generator block diagram figure 131. counter timing chart figure 132. yflag timing chart c2fx 8bit counter rfck h80 yflag comp c2fx rfck counter c2fx counter 8bit yflag hff h80 h00 downloaded from: http:///
256/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 17.3.24. a precaution in pcb layout. (recommendation) ? put on bypass condenser 0.1uf and about 10uf to 100uf in as cl ose a position as possible between vdd which is a pair, and gnd in the ic. ? put on bypass condenser of about 10uf in the vbias terminal surely. ? each vdd-gnd of rf of the ic and digital surely separates, and does a ground one point from the supply cause of th e power supply. ? connect the parts with the outside connected with vdd and gnd with vdd with the relations and gnd. ? show an attention point about pre-servo amplifier (rf) part and the audio part in the bottom figure. acbd layout an input resistor to ac, bd as mach as possible near the terminal. asy agnd1 eqo rfi layout a condenser as much as possible near the terminal. downloaded from: http:///
257/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 17.4. i/o signals pin name i/o function destination clk_i in apb bus clock clkctr rstb_i in reset (active low) rstgen paddr_i in apb bus address apb penable_i in apb bus enable apb pwdata_i in apb bus write data apb pwrite_i in apb bus write enable apb psel_i in apb bus select apb prdata _o out apb bus read data apb ac in a ? c voltage input pad bd in b+d voltage input pad vbias out bias level pad e in e voltage input pad f in f voltage input pad pd in apc photo detector input pad ld out apc laser drive output pad asy out asymmetric correction pad pco out pll pco output pad fco out pll fco-dac output pad fdout out focus drive output pad tdout out tracking drive output pad sdout out sled drive output pad clvout out clv drive output pad rfi in rf output capacitance coupling re-input pad eqo out output after rf equalizer pad ad_moni0 inout input & monitor signal output pad ad_moni1 inout input & monitor signal output pad ana_moni0 inout input & analog monitor output pad ana_moni1 inout input & analog monitor output pad cddsp_clk_i in cd-dsp clock (16.9344 mhz) clkctr clr_i in cd-dsp reset (active high) rstgen lrck_o out signal used to switch between lch and rch for ecc data output i2s_in bck_o out signal synchronized with data_o outputted from ecc i2s_in data_o out 16-bit cd data outputted from ecc block i2s_in subsyq_o out subcode block sync signal i2s_in wfck_o out subcode frame sync signal i2s_in subck_i in subcode shift clock signal i2s_in subdata_o out subcode data signal i2s_in clk88_o out driver clk and external circuit clk pinctr downloaded from: http:///
258/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 17.5. register 17.5.1. memory map name description address offset width reset cd-dsp_write_set set cd-dsp write command 0x00 16 16h0000 cd-dsp_write_comp completion cd-dsp write command 0x04 32 32h00000000 cd-dsp_read_set set cd-dsp read command 0x08 8 8h00 cd-dsp_read_dat read data cd-dsp read command 0x0c 32 32h00000000 cd-dsp_status_set set cd-dsp read status 11 byte 0x10 8 8h00 cd-dsp_status_dat read data cd-dsp read status 0x14 32 32h00000000 cd-dsp_subq_set set cd-dsp read status and subq 0x18 8 8h00 cd-dsp_subq_dat0 read data cd-dsp read subq_0 0x1c 32 32h00000000 cd-dsp_subq_dat1 read data cd-dsp read subq_1 0x20 32 32h00000000 cd-dsp_subq_dat2 read data cd-dsp read subq_2 0x24 32 32h00000000 for commands to cd-dsp, refer to 17.5.5 cd-dsp command. downloaded from: http:///
259/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 17.5.2. register detail cd-dsp_write_set offset: 0x00 width:16 bits bits name direction reset description 15:8 write address w 0x00 cd-dsp write address 7:0 write data w 0x00 cd-dsp write data for commands to cd-dsp, refer to 17.5.5 cd-dsp command. cd-dsp_write_comp offset: 0x04 width:32 bits bits name direction reset description 31:17 r 0x00 16 completion write r 0x01 command write completion bit 0: write not completed 1: write completed 15:8 wants to write address r 0x00 cd-dsp write address 7:0 wants to write data r 0x00 cd-dsp write data cd-dsp_read_set offset: 0x08 width: 8 bits bits name direction reset description 15:8 read address w 0x00 cd-dsp read address 7:0 0x00 for commands to cd-dsp, refer to 17.5.5 cd-dsp command. cd-dsp_read_dat offset: 0x0c width:32 bits bits name direction reset description 31:17 r 0x00 16 completion read r 0x01 command read completion bit 0: data acquisition not completed 1: data acquisition completed 15:8 wants to read address r 0x00 cd-dsp read address 7:0 wants to read data r 0x00 cd-dsp read data if data acquisition has not been completed, 0x00 is read. cd-dsp_status_set offset: 0x10 width: 8 bits bits name direction reset description 7:1 0x00 0x00 0 read status w 0x00 cd-dsp read status execute only by write operation. for cd-dsp statuses, refer to information in 17.5.3.read cd-dsp status downloaded from: http:///
260/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 cd-dsp_ status _dat offset: 0x14 width:32 bits bits name direction reset description 31 0x00 0x00 30 yflag r 0x00 cd-dsp yflag signal 29 subsyq r 0x00 cd-dsp subsyq signal 28 busy r 0x00 cd-dsp busy signal 27:25 0x00 24 completion status r 0x01 status acquisition completion bit 0: data acquisition not completed 1: data acquisition completed 23:16 cd-dsp status r 0x00 cd-dsp status if data acquisition has not been completed, 0x00 is read. 15:0 0x00 cd-dsp_ subq _set offset: 0x18 width: 8 bits bits name direction reset description 7:1 0x00 0x00 0 read status w 0x00 when this bit is seto to 1, read status and sub-q from cd-dsp is executed. execute only by write operation. for cd-dsp statuses, refer to information in 17.5.3.read cd-dsp status cd-dsp_ subq _dat0 offset: 0x1c width:32 bits bits name direction reset description 31 0x00 0x00 30 yflag r 0x00 cd-dsp yflag signal 29 subsyq r 0x00 cd-dsp subsyq signal 28 busy r 0x00 cd-dsp busy signal 27:25 0x00 24 completion subq r 0x01 sub-q acquisition completion bit 0: data acquisition not completed 1: data acquisition completed 23:16 cd-dsp status r 0x00 cd-dsp status if data acquisition has not been completed, 0x00 is read. 15:8 sub-q 1 r 0x00 1st byte of sub-q data if data acquisition has not been completed, 0x00 is read. 7:0 sub-q 2 r 0x00 2nd byte of sub-q data if data acquisition has not been completed, 0x00 is read. cd-dsp_ subq _dat1 offset: 0x20 width:32 bits bits name direction reset description 31:24 sub-q 3 r 0x00 3rd byte of sub-q data if data acquisition has not been completed, 0x00 is read. 23:16 sub-q 4 r 0x00 4th byte of sub-q data if data acquisition has not been completed, 0x00 is read. 15:8 sub-q 5 r 0x00 5th byte of sub-q data if data acquisition has not been completed, 0x00 is read. 7:0 sub-q 6 r 0x00 6th byte of sub-q data if data acquisition has not been completed, 0x00 is read. downloaded from: http:///
261/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 cd-dsp_ subq _dat2 offset: 0x24 width:32 bits bits name direction reset description 31:24 sub-q 7 r 0x00 7th byte of sub-q data if data acquisition has not been completed, 0x00 is read. 23:16 sub-q 8 r 0x00 8th byte of sub-q data if data acquisition has not been completed, 0x00 is read. 15:8 sub-q 9 r 0x00 9th byte of sub-q data if data acquisition has not been completed, 0x00 is read. 7:0 sub-q 10 r 0x00 10th byte of sub-q data if data acquisition has not been completed, 0x00 is read. downloaded from: http:///
262/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 17.5.3. cd-dsp status cd-dsp status 8bit that it begins to be read by bit [23:16] of cd-dsp_status_dat is shown in the following. bit name description lsb gfs h if detected synchronously (11t, 11t, 2t) 1 fok h if focused perfectly 2 wq h if crc check is ok 3 sens h if somewhat error is detected during measurement for auto adjustment 4 busy l while measurening for auto adjustment and track jumping 5 f_loopon h if focus loop closed 6 fsdown h when search voltage is in the section of reduction in focus searching msb fsfzc h if fzc detected while focus search downloaded from: http:///
263/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 17.5.4. inside signal monitor output 43pin ana_moni0 44pin ana_moni1 47pin ad_moni0 48pin ad_moni1 the inout of the analog or digital inside signal of the cd-dsp block can be done more than upper 4 terminal. digital signal output switching commnad b0x0 b0x1 b0x2 b0x3 47 ad_moni0 pcpi wfck c2fx c2fx 48 ad_moni1 pcni rfck wq c1f2 43 ana_moni0 gfs di sk_syq subsyq c2f1 44 ana_moni1 rfck wq wfck c2f commnad b0x4 b0x5 b0x6 b0x7 47 ad_moni0 lrck(ecc) - frame[2] sfpl 48 ad_moni1 c2f hokan_flag frame[3] fok 43 ana_moni0 c2clk yflag slow_fast busy 44 ana_moni1 hokan_fla g rfck sfpl clk3k commnad b0x8 b0x9 b0xa b0xb 47 ad_moni0 tj_sig scrtimer sens sfpl 48 ad_moni1 busy fok busy fok 43 ana_moni0 clv_busy comp dout busy 44 ana_moni1 scrtimer tguon scrtimer subsyq commnad b0xc b0xd b0xe b0xf 47 ad_moni0 sfpl w_latch c2fx 48 ad_moni1 fok c2fx yflag 43 ana_moni0 slow_fast status_sel hokan_flag 44 ana_moni1 mirror efm2 c2fx pcpi pcpi is the signal to synchronize phases of the efm signal and the plck signal. it makes pco signal together with the pcni signal. for the details, refer to the item of clv and pll. pcni pcni is the signal to synchronize phases of the efm signal and the plck signal. it makes pco signal together with the pcpi signal. for the details, refer to the item of clv and pll. gfs gfs is the signal to monitor whether the synchronizing signal of disc was detected correctly. it turns to h if the synchronizing signal and 588 count of plck are in agreement. for the details, refer to the item of window. rfck rfck is the frame clock generated on the basis of xin. for the details, refer to the item of window. wfck wfck is the frame clock generated on the basis of the efm signal. for the details, refer to the item of window. disc_syq disc_syq is the signal which turns to h when the synchronizing signal of disc was detected. wq wq is the signal which turns to h when crc check is ok. for the details, refer to the item of reading internal status and sub-q code. c2fx c2fx is the signal which turns to h when c2 series cannot be corrected by error correction of an one-frame unit. c1f2 please refer to the error correction (ecc) part for c1 series correction flag. c2f c2f is the flag which shows the data interpolation situation of douta. when c2f is h, it shows that the data is uncorrectable data. for the details, refer to the item of error correcter (ecc). lrck(ecc) it is the signal for the lch/rch change at the time of the ecc data output. for the details, refer to the item of error correcter (ecc). hokan_flag it is the flag shows linear interpolation situation. if it is h, it is shown that the linear interpolation of the data is impossible for continuous correction impossible data from ecc output. frame[3:0] it is the signal for counting frames. for the details, refer to the item of error correcter (ecc). slow/fast it shows the result of count between the edges of efm in plck. it turns to l if counted value is no more than 11t and turns to h if counted value is more than 11t. for the details, refer to the item of clv and pll. sfpl sfpl is the signal which turns to l when the pll operation mode is normal initialize mode and turns to h when the mode is normal pc mode or wide mode. fok fok is the signal which turns to h when focus suits. for the details, refer to the item of focus search. scrtimer scrtimer is the signal adding defect and new_defect. if it turns h, it turns to l after 4ms passed. comp comp is the output of the result of comparison at adjustment of balance and gain of tracking and focus. tguon tguon is the signal which turns to h when the gain of tracking filter increases at track jumping and etc. sens sens is the signal which turns to h if errors are exist during auto adjustment. for the details, refer to the item of auto adjustment and measurement. dout(subq) it is the signal to read internal status and sub-q code. for the details, refer to the item of command interface. mirror mirror is the signal which turns to h when laser passed through the mirror side. for the detailes, refer to the item of mirror signal generator. downloaded from: http:///
264/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 (analog signal) by command &h63[7:0], 43, 44pin are available for monitoring various internal signals and for inputting the test signal. 43pin ana_moni0 command meaning &h631x da output of digital signals &h632x asy output &h633x ac amplifier output &h634x acbd amplifier output &h635x acbd input & separation &h636x dac output of det block &h637x fe(ac) output &h638x fe(bd) input & separation &h639x te(e) output &h63ax te(f) input & separation &h63bx apcref output &h63cx bg output &h63dx adpf amplifier output &h63ex adpf input & separation &h63fx rvco voltage output &h6307 dac output of adc block 44pin ana_moni1 command meaning &h63x1 da output of digital signals &h63x2 bd amplifier output &h63x3 fe(ac) input & separation &h63x4 fe(bd) output &h63x5 te(e) input & separation &h63x6 te(f) output 43,44pin are i/o terminals with built-in pull-up resistor. execute monitor setup for these terminals by the following commands. &hb4[7:6] change-over of monitor terminal digital/analog &hb5[7:6] on/off of pull-up resistor built in monitor terminal the contents of each signal are as follows. asy output: it is the output of asy block of rf block. ac amplifier output: it is the output of the first amplifier by the side of ac input of the rf block. acbd amplifier output: it is the output of the addition amplifier of ac signal and bd signal. acbd input & separation: it separates the output of acbd side ac, bd addition amplifier and it is made to input from the outside. by this, it is possible to input to rfgca directly. dac output of det block: it is the output of the 6bitdac which becomes to threshold level of compersion at det circuit in rf block. fe(ac) output: it is the output of ac side fe amplifier. fe(bd) input & separation: it separates the output of bd side fe amplifier and it is made to input from the outside. by this, i t is possible to input to adc directly. te(e) output: it is the output of e side of te amplifier. te(f) input & separation: it separates the output of f side te amplifier and it is made to input from the outside. by this, it is possible to input to adc directly. apcref output: it outputs the ref voltage of apc circuit. it is possible to monitor the reference level of apc. bg output: it outputs the bg voltage of apc circuit. adpf amplifier output: it is the output of the addition amplifier of pco signal and fco signal of the pll block. adpf input & separation: it separates the input of the addition amplifier of pco signal and fco signal of the pll block. it is possible to input to the addition amplifier from the outside directly. rvco voltage output: it outputs rvco voltage of pll block. this voltage is used for set value of vco offset. dac output of adc block: it is the output of the dac for set up the reference voltage in a/d converter of servo system. bd amplifier output: it is the output of the first amplifier by the side of bd input of the rf block. fe(ac) input & separation: it separates the output of ac side fe amplifier and it is made to input from the outside. by this, i t is possible to input to adc directly. fe(bd) output: it is the output of bd side fe amplifier. te(e) input & separation: it separates the output of e side te amplifier and it is made to input from the outside. by this, it is possible to input to adc directly. te(f) output: it is the output of f side te amplifier. downloaded from: http:///
265/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 (da output of digital signals) it is possible to monitor the signals calculated by the digital block from 43pin and 44pin by commands &h631x and &h63x1 as analog output through dac. the signal to monitor is selectable by command &hfa[3:0]. &hfa[3:0] 43pin ana_moni0 44pin ana_moni1 0h fe te 1h sled_hpf lpf 2h rfrp tzc 3h bl pl 4h ps bs 5h ps pl 6h bl bs 7h te e+f_hpf 8h - sled 43, 44pin are i/o terminals with built-in pull-up resistor. execute monitor setup for these terminals by the following commands. &hb4[7:6] change-over of monitor terminal digital/analog &hb5[7:6] on/off of pull-up resistor built in monitor terminal the contents of each signal are as follows. fe: it is the focus error signal. it is made by subtracting with ac signal and bd signal. sled_hpf: it is the hpf componet of sled signal. it is used for adjustment of sled gain. rfrp: it is the signal made by subtracting peak_short signal and bottom_short signal of rf signal. for the details, refer to the item of rfrp signal generator. bl: it is the bottom_logn signal of rf signal. for the details, refer to the item of det circuit. ps: it is the peak_short signal of rf signal. for the details, refer to the item of det circuit. te: it is the tracking error signal. it is made by subtracting with e signal and f signal. lpf: it is the output of each lpf and bpf used for auto adjustment. for the details, refer to the each item of auto adjustment and measurement. tzc: it is the hpf component of te signal. tzc signal is generated by compared this signal with 0 and used for tr number counting at the time of track jump. pl: it is the peak_long signal of rf signal. for the details, refer to the item of det circuit. bs: it is the bottom_short signal of rf signal. for the details, refer to the item of det circuit. e+f_hpf: it is the hpf component of (e+f) signal. sled: it is the sled error signal. downloaded from: http:///
266/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 17.5.5. cd-dsp command BM94801KUT instruction codes list msb/lsb 0 1 2 3 4 5 6 7 4 power down power down system clock yflag count1 5 pll vco dev efm dev pll setting pll test setting 6 rf laser on eq apc rf gain apc ref rf-eq setting rf test setting rf-ac offset rf-bd offset rf-e offset rf-f offset 7 8 clv pll clv mode setting clv-w target pll mode setting clv setting fc gain pci gain clv gain clv-w gain clv-n gain clv, pll t-gain 9 offse t sled offset focus offset tracking offset ac amp offset bd amp offset e amp offset f amp offset a circ audio att ecc status defect n-defect win, sub test subq test b moni m o n i i / o select moni d/ a select moni pu on/off pio setting pio out register c servo seq fon servo test tr on sled on tr jump forward sd move forward tr jump reverse sd move reverse d servo seq adj go adj sled gain adj wait time tr error min-max tr error number &hde read setting dfct, n-dfct setting 1 dfct, n-dfct setting 2 e servo df f servo df intermittent sled on intermittent sled off fzc level ats level sled gain setting sled lps setting fe, te offset tzc filter msb/lsb 8 9 a b c d e f 4 power down yflag count2 yflag count3 5 pll i d r e a d 6 rf fe-gain setting adc full setting 7 8 clv pll clv kick pci counter clv, pll setting clv,pll test-reg a ts time setting hpf(e+f) setting 9 offse t fo balance offset tr balance offset fo total gain tr total gain rf offset rf gain vco center vco gain a circ rf-det setting 1 deffect th level fok setting rf-det setting 2 rf-det setting 3 b moni c servo seq fo serch voltage focus loop loop off recovery tr jump setting tr jump bt,ot tr jump ls kick t ats setting servo setting d servo seq seq test seq moni adj sq status e servo df fo lpf hpf gain fo filter setting tr lpf hpf gain tr filter setting fo, tr gain disturbance setting monitor setting gain down sled select f servo df f/e gain-down tdout offset monitor select asy offset tr jump pulse add tr jump pulse-h sled pulse-h downloaded from: http:///
267/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 command : &h40 mean ing : power down setting (initial value : 00h) bit command code meaning status msb pwdrf rf power down. (others than bias voltage generation circuit) 0 : normal (initial value) 1 : power down 6 pwdbi rf bias voltage generation circuit power down. 0 : normal (initial value) 1 : power down 5 pwdse servo power down. 0 : normal (initial value) 1 : power down 4 pwdadc adc power down. 0 : normal (initial value) 1 : power down 3 - 2 - 1 pwdadp adpfo power down. 0 : normal (initial value) 1 : power down lsb pwdana aoudio lineout power down. 0 : normal (initial value) 1 : power down command : &h41 meaning : system clock setting (initial value : 00h) bit command code meaning status msb dfclk df system clock. 0 : normal (initial value) 1 : stop 6 audclk audio system clock. 0 : normarl (initial value) 1 : stop 5 - 4 eccclk ecc system clock. 0 : normal (initial value) 1 : stop 3 17mclk clk17m system clock. 0 : normal (initial value) 1 : stop 2 adlclk adc logic system clock. 0 : normal (initial value) 1 : stop 1 clvclk clv logic system clock. 0 : normal (initial value) 1 : stop lsb delclk det logic system clock. 0 : normal (initial value) 1 : stop downloaded from: http:///
268/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 command : &h47 meaning : yflag counter setting (initial value : 08h) bit command code meaning status msb cnten to select yflag counter enable. 0 : counter off (initial value) 1 : counter on 6 outen to select yflag output invert. 0 : normal (initial value) 1 : invert 5 flg_ sel1 to select yflag output. 0 : counter (initial value) 1 : hokan_flag 2 : c2fx 3 : external 4 flg_ sel0 3 hout to fix output to h. 0 : normal 1 : h (initial value) 2 lout to fix output to l. 0 : normal (initial value) 1 : l 1 - lsb cntio_ sel to input counter signal from external terminal. 0 : internal (c2fx) (initial value) 1 : external command : &h48 meaning : yflag counter count-up setting (initial value : 08h) bit command code meaning status msb cntup7 to set yflag counter count up value. (initial value : 08h) 6 cntup6 5 cntup5 4 cntup4 3 cntup3 2 cntup2 1 cntup1 lsb cntup0 downloaded from: http:///
269/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 command : &h49 meaning : yflag counter count-down settting (initial value : 08h) bit command code meaning status msb cntdw7 to set yflag conter count down value. (initial value : 08h) 6 cntdw6 5 cntdw5 4 cntdw4 3 cntdw3 2 cntdw2 1 cntdw1 lsb cntdw0 command : &h50 meaning : pll setting, efm dividing ratio (initial value : 00h) (recommended value : 80h) bit command code meaning status msb dvco1 to set vco-pc dividing ratio. 0 : 1/1 (initial value) 1 : 1/2 2 : 1/4 3 : 1/8 6 dvco0 5 defm1 to set efm dividing ratio. 0 : 1/1 (initial value) 1 : 1/2 2 : 1/4 3 : 1/8 4 defm0 3 - 2 - 1 - lsb - downloaded from: http:///
270/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 command : &h51 meaning : various setting items for pll (initial value : c2h) (recommended value : 00h) bit command code meaning status msb selx to select external input for plck. be sure to set up 0 when using normal operation. 0 : normal 1 : external input (initial value) 6 vcostp to turn on/off vco transmitter. be sure to set up 0 when using normal operation. 0 : on 1 : off (initial value) 5 pcom1 pco condition in defect. 0 : with compensation (initial value) 1 : hi-z 2 : without countermeasure 4 pcom0 3 vco out to input vco output from ac terminal (mirror). 0 : normal (initial value) 1 : test 2 plck rev to invert plck input. 0 : normal (initial value) 1 : invert 1 efmext external input for efm. be sure to set up 0 when using normal operation. 0 : normal 1 : input (initial value) lsb dac load to load the value of command &h91[7:0],&h92[7:6] to dac of adc block. (use only at the time of test) 0 : normal (initial value) 1 : load command : &h52 meaning : pll test setting (initial value : 00h) bit command code meaning status msb selfco to select fco. 0 : on (initial value) 1 : hiz 6 asyofs to select asy offset. 0 : hiz (initial value) 1 : on 5 asyhiz to select the conditi on which sets asy to hiz. 0 : when fok is l (initial value) 1 : when fok is l or defect is h 4 pllpch to select the signal which holds pll_pc. 0 : when new_defect is h (initial value) 1 : when defect or new_defect is h 3 - 2 - 1 - lsb pllpchl to hold pll_pc(pcpi=l,pcni=l) 0:normal (initial value) 1:hold downloaded from: http:///
271/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 command : &h5e meaning : model id (exclusive for reading) bit command code meaning status msb id7 to read id number of application model. in case of BM94801KUT 47h 6 id6 5 id5 4 id4 3 id3 2 id2 1 id1 lsb id0 command : &h60 meaning : laser on (initial value : 00h) (recommended value : 10h) bit command code meaning status msb - 6 - 5 - 4 lon to turn on the laser. 0 : laser off (initial value) 1 : laser on 3 - 2 eqtest eq test. 0 : normal (initial value) 1 : to change eqo terminal for input pin 1 rffc_ sel to select rf amplifier (first step) phase compensateing capacitors. 0 : 0.25pf (initial value) 1 : 0.125pf lsb apcinv to select apc polarity setting. 0 : normal (initial value) 1 : invert downloaded from: http:///
272/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 command : &h61 meaning : focus/tracking gain setting and apc ref voltage setting (initial value : 07h) bit command code meaning status msb - 6 - 5 cdrw_ sel1 to set focus/tracking gain. ( rf, fe / te ) 0 : normal cd (1/1) (initial value) 1 : rw high refracction (3/3) 2 : rw normal (5/3) 4 cdrw_ sel0 3 apcref _sel3 to set apc ref voltage. &h61[3:0] ? 5+145 [mv] (vcc=3.0v) 2 apcref _sel2 1 apcref _sel1 lsb apcref _sel0 command : &h62 meaning : rf equalizer setting (initial value : 09h) bit command code meaning status msb - 6 - 5 eqf_ sel1 to set rf equalizer frequency. 0 : 0.72mhz (initial value) 1 : 1.45mhz 2 : 2.90mhz 3 : eq through 4 eqf_ sel0 3 eqg_ sel1 to set rf equalizer gain. 0 : 6db 1 : 9db 2 : 12db (initial value) 2 eqg_ sel0 1 eqb_ sel1 to select rf equalizer boost level. 0 : 2db 1 : 4db (initial value) 2 : 6db 3 : 8db lsb eqb_ sel0 downloaded from: http:///
273/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 command : &h63 meaning : rf test setting (initial value : 00h) bit command code meaning status msb ana_m 03 used for rf chip test.(ana-moni0) 0h : normal (initial value) 1h : moni0_test (da output of digital signals) 2h : asy_test (asy output) 3h : ac_test (ac amplifier output) 4h : acbd_test (acbd amplifier output) 5h : acbd_test (acbd input & separation) 6h : det_test (dac output of det block) 7h : fe_test_ac (fe (ac) output) 8h : fe_cut_bd (fe (bd) input & separation) 9h : te_test_e (te (e) output) ah:te_cut_f (te (f) input & separation) bh: apcref_test (apcref output) ch: bg_test (bg output) dh:loop_test[2] (adpf amplifier output) eh:loop_test[1] (adpfinput & separation) fh:loop_test[0] (rvco voltage block) 6 ana_m 02 5 ana_m 01 4 ana_m 00 3 - &h6307h : adc_test (dac output of adc block) ana_moni0 2 ana_m 12 used for rf chip test.(ana-moni1) 0h : normal (initial value). 1h : moni1_test (da output of digital signals) 2h : bd_test (bd amplifier output) 3h : fe_cut_ac (fe (ac) input & separation) 4h : fe_test_bd (fe (bd) amplifier output) 5h : te_cut_e (te (e) input & separation) 6h : te_test_f (te (f) output) 1 ana_m 11 lsb ana_m 10 command : &h64 meaning : ac amplifier offset adjustment (initial value : 04h) bit command code meaning status msb - 6 - 5 - 4 - 3 - 2 ac_off set2 ac amplifier offset adjustment. vc-{&h64[2:0] ? (-0.22) ? v dd /3} (initial value : 04h) 1 ac_off set1 lsb ac_off set0 downloaded from: http:///
274/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 command : &h65 meaning : bd amplifier offset adjustment (initial value : 04h) bit command code meaning status msb - 6 - 5 - 4 - 3 - 2 bd_off set2 bd amplifier offset adjustment. vc-{&h65[2:0] ? (-0.22) ? v dd /3} (initial value : 04h) 1 bd_off set1 lsb bd_off set0 command : &h66 meaning : e amplifier offset adjustment (initial value : 04h) bit command code meaning status msb - 6 - 5 - 4 - 3 - 2 e_off set2 e amplifier offset adjustment. vc+{(7-&h66[2:0]) ? 0.22 ? v dd /3} (initial value : 04h) 1 e_off set1 lsb e_off set0 downloaded from: http:///
275/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 command : &h67 meaning : f amplifier offset adjustment (initial value : 04h) bit command code meaning status msb - 6 - 5 - 4 - 3 - 2 f_off set2 f amplifier offset adjustment. vc+{(7-&h67[2:0]) ? 0.22 ? v dd /3} (initial value : 04h) 1 f_off set1 lsb f_off set0 command : &h68 meaning : focus error gain setting (initial value : 0bh) bit command code meaning status msb - 6 - 5 - 4 - 3 fe_ga in3 fe gain setting. 0h : 0.37[db] 1h : 0.75[db] 2h : 1.16[db] 3h : 1.58[db] 4h : 2.03[db] 5h : 2.50[db] 6h : 3.00[db] 7h : 3.50[db] 8h : 4.08[db] 9h : 4.68[db] ah : 5.32[db] bh : 6.00[db] (initial value) ch : 6.77[db] dh : 7.60[db] eh : 8.32[db] fh : 9.54[db] 2 fe_ga in2 1 fe_ga in1 lsb fe_ga in0 downloaded from: http:///
276/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 command : &h69 meaning : adc block dynamic range select (initial value : 00h) bit command code meaning status msb adcfr adc full range. 0 : normal (initial value) 1 : full range 6 adcch_ sel2 adc full range channel. 0 : 0ch (initial value) 1 : 1ch 2 : 2ch 3 : 3ch 4 : 4ch 5 : 5ch 6 : all 7 : nothing 5 adcch_ sel1 4 adcch_ sel0 3 - 2 - 1 - lsb - command : &h80 meaning : clv servo mode setting (initial value : 00h) (recommended value : 40h) bit command code meaning status msb - 6 clv mode2 to set clv servo run mode. 0 : off (initial value) 1 : kick (&h88 setup value output. positive voltage output) 2 : brake (&h88 setup value output. negative voltage output) 3 : auto stop 4 : on (shift to auto) 5 : phase mode 6 : rough mode 7 : high speed rough mode 5 clv mode1 4 clv mode0 3 - 2 - 1 - lsb - downloaded from: http:///
277/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 command : &h81 meaning : target setting under clv wide mode (initial value : 00h) bit command code meaning status msb tar7 to set upper 8bits of target value under clv wide mode. (approx. 1 speed by 1eh, approx speed by 3dh,approx. 4 speed by 7ah.) (initial value : 00h) 6 tar6 5 tar5 4 tar4 3 tar3 2 tar2 1 tar1 lsb tar0 command : &h82 meaning : pllmode setting (initial value : 00h) (recommended value : 10h) bit command code meaning status msb - 6 - 5 pllmod1 to set pll run mode. 0 : initialize mode (initial value) 1 : normal pc mode 2 : wide mode 3 : 4 speed mode (for vco mesurement) 4 pllmod0 3 - 2 - 1 - lsb - downloaded from: http:///
278/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 command : &h83 meaning : clv setting and fc integral gain (initial value : 00h) (recommended value : 01h) bit command code meaning status msb - 6 hcoe to turn on/off half-wave clv mode. 0 : off (initial value) 1 : on 5 clvhit1 to set clv height restrictions. 0 : no restriction (initial value) 1 : 1/8 2 : 2/8 3 : 3/8 4 clvhit0 3 - 2 h5n2 fc integral gain. 2 -n (n : setup value) initial value : 2 -0 =1 1 h5n1 lsb h5n0 command : &h84 meaning : pci integral gain, clv phase gain (initial value : 00h) (recommended value : 53h) bit command code meaning status msb - 6 h5p2 pci integral gain. 2 -n (n : setup value) initial value : 2 -0 =1 5 h5p1 4 h5p0 3 - 2 h1n2 clv phase gain. 2 -n (n : setup value) initial value : 2 -0 =1 1 h1n1 lsb h1n0 downloaded from: http:///
279/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 command : &h85 meaning : gain under clv wide (initial value : 00h) (recommended value : 34h) bit command code meaning status msb - 6 h2w2 low boost gain under clv_wide. 2 -n (n : setup value) initial value : 2 -0 =1 5 h2w1 4 h2w0 3 - 2 h4w2 through gain under clv_wide. 2 -n (n : setup value) initial value : 2 -0 =1 1 h4w1 lsb h4w0 command : &h86 meaning : gain under clv normal (initial value : 00h) (recommended value : 31h) bit command code meaning status msb - 6 h2n2 low boost gain under clv-normal. 2 -n (n : setup value) initial value : 2 -0 =1 5 h2n1 4 h2n0 3 - 2 h4n2 through gain under clv-normal. 2 -n (n : setup value) initial value : 2 -0 =1 1 h4n1 lsb h4n0 downloaded from: http:///
280/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 command : &h87 meaning : clv and pll total gain (initial value : 00h) bit command code meaning status msb cng gain under clv-normal. 0 : 1 (initial value) 1 : 0.75 6 cwg gain under clv-wide. 0 : 1 (initial value) 1 : 0.75 5 cpg clv phase gain. 0 : 1 (initial value) 1 : 0.75 4 fcg fc gain. 0 : 1 (initial value) 1 : 0.75 3 pcg pci gain. 0 : 1 (initial value) 1 : 0.75 2 - 1 - lsb - command : &h88 meaning : clv kick height (initial value : 7fh) bit command code meaning status msb cvk7 clv kick height (value : complement for 2). (initial value : 7fh) 6 cvk6 5 cvk5 4 cvk4 3 cvk3 2 cvk2 1 cvk1 lsb cvk0 downloaded from: http:///
281/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 command : &h89 meaning : pci counter initial value (initial value : 00h) bit command code meaning status msb pcintv7 to set initial value of pci counter. (initial value : 00h) 6 pcintv6 5 pcintv5 4 pcintv4 3 pcintv3 2 pcintv2 1 pcintv1 lsb pcintv0 command : &h8a meaning : clv,pllstatus setting (initial value : 00h) bit command code meaning status msb sel clvh clv status against focusing failure. 0 : vc output (initial value) 1 : without counter measure 6 int_l to load pll integral register value. 0 : normal (initial value) 1 : &h8b[7 : 0] setup value is loaded 5 tofs to set whether to add offset to the change in target value. 0 : add (initial value) 1 : dont add 4 - 3 jclvh to set whether to carry out clv hold at lock h and under track jump. 0 : dont add (initial value) 1 : add 2 dclvh to set whether to carry out clv hold at lock h and under defect h. 0 : dont add (initial value) 1 : add 1 ndclv hm to set whether to carry out clv hold at lock h under new_defect h. 0 : dont add (initial value) 1 : add lsb - downloaded from: http:///
282/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 command : &h8b meaning : clv and pll test input register (initial value : 00h) bit command code meaning status msb cptst7 to register clv/pll test inputs. (center value : 00h) (initial value : 00h) 6 cptst6 5 cptst5 4 cptst4 3 cptst3 2 cptst2 1 cptst1 lsb cptst0 command : &h8c meaning : gain up hold time setting (initial value : 00h) bit command code meaning status msb - 6 gainup hld2 to select hold time of gain up when anti-shock. 0 : 0ms (initial value) 1 : 20ms 2 : 50ms 3 : 100ms 4 : 200ms 5 gainup hld1 4 gainup hld0 3 - 2 - 1 - lsb - downloaded from: http:///
283/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 command : &h8d meaning : hpf(e+f) signal reverse setting (initial value : 00h) bit command code meaning status msb 6 5 4 3 2 1 lsb eaf rever hpf(e+f) signal reverse. 0 : normal (initial value) 1 : reverse command : &h91 meaning : sled offset adjusting register (initial value : 80h) bit command code meaning status msb sdofs7 to adjust sled offset. center value is 80h because of offset binary. (initial value : 80h) 6 sdofs6 5 sdofs5 4 sdofs4 3 sdofs3 2 sdofs2 1 sdofs1 lsb sdofs0 downloaded from: http:///
284/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 command : &h92 meaning : focus offset adjusting register (initial value : 80h) bit command code meaning status msb fdofs7 to adjust focus offset. center value is 80h because of offset binary. (initial value : 80h) 6 fdofs6 5 fdofs5 4 fdofs4 3 fdofs3 2 fdofs2 1 fdofs1 lsb fdofs0 command : &h93 meaning : tracking offset adjusting register (initial value : 80h) bit command code meaning status msb tdofs7 to adjust tracking offset. center value is 80h because of offset binay. (initial value : 80h) 6 tdofs6 5 tdofs5 4 tdofs4 3 tdofs3 2 tdofs2 1 tdofs1 lsb tdofs0 downloaded from: http:///
285/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 command : &h94 meaning : ac amplifier of rf block offset adjusting register (initial value : 80h) bit command code meaning status msb acofs7 to adjust offset of ac amplifier of rf block. center value is 80h because of offset binary. (initial value : 80h) 6 acofs6 5 acofs5 4 acofs4 3 acofs3 2 acofs2 1 acofs1 lsb acofs0 command : &h95 meaning : bd amplifier of rf block offset adjusting register (initial value : 80h) bit command code meaning status msb bdofs7 to adjust offset of bd amplifier of rf block. center value is 80h because of offset binary. (initial value : 80h) 6 bdofs6 5 bdofs5 4 bdofs4 3 bdofs3 2 bdofs2 1 bdofs1 lsb bdofs0 downloaded from: http:///
286/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 command : &h96 meaning : e amplifier of rf block offset adjusting register (initial value : 80h) bit command code meaning status msb rfeofs7 to adjust offset of e amplifier of rf block. center value is 80h because of offset binary. (initial value : 80h) 6 rfeofs6 5 rfeofs5 4 rfeofs4 3 rfeofs3 2 rfeofs2 1 rfeofs1 lsb rfeofs0 command : &h97 meaning : f amplifier of rf block offset adjusting register (initial value : 80h) bit command code meaning status msb rffofs7 to adjust offset of f amplifier of rf block. center value is 80h because of offset binary. (initial value : 80h) 6 rffofs6 5 rffofs5 4 rffofs4 3 rffofs3 2 rffofs2 1 rffofs1 lsb rffofs0 downloaded from: http:///
287/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 command : &h98 meaning : focus balance offset adjusting register (initial value : 80h) bit command code meaning status msb fbofs7 to adjust focus balance offset. center value is 80h because of offset binary. (initial value : 80h) 6 fbofs6 5 fbofs5 4 fbofs4 3 fbofs3 2 fbofs2 1 fbofs1 lsb fbofs0 command : &h99 meaning : tracking balance offset adjusting register (initial value : 80h) bit command code meaning status msb tbofs7 to adjust tracking balance offset. center value is 80h because of offset binary. (initial value : 80h) 6 tbofs6 5 tbofs5 4 tbofs4 3 tbofs3 2 tbofs2 1 tbofs1 lsb tbofs0 downloaded from: http:///
288/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 command : &h9a meaning : focus total gain adjusting register (initial value : 10h) bit command code meaning status msb - 6 - 5 fg5 to adjust focus total gain. center value is 20h because of offset binary. &h9a[5 : 0] multiple (initial value : 10h) 4 fg4 3 fg3 2 fg2 1 fg1 lsb fg0 command : &h9b meaning : tracking total gain adjusting register (initial value : 10h) bit command code meaning status msb - 6 - 5 tg5 to adjust tracking total gain. center value is 20h because of offset binary. &h9b[5:0] multiple (initial value : 10h) 4 tg4 3 tg3 2 tg2 1 tg1 lsb tg0 downloaded from: http:///
289/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 command : &h9c meaning : rf offset adjusting register (initial value : 08h) bit command code meaning status msb - 6 - 5 - 4 - 3 rfofs3 to adjust rf offset (rf basic level). vc+((15-&h9c[3:0]) ? 0.20-2.0) ? v dd /3 [v] (initial value : 08h) 2 rfofs2 1 rfofs1 lsb rfofs0 command : &h9d meaning : rf gain adjusting register (initial value : 1ah) bit command code meaning status msb - 6 - 5 - 4 rfgain4 to adjust rf gain. however, the range which may be taken by &h9d[4 : 0] is taken as from 00h to 1fh. 100/ ( (31-&h9d[4:0]) ? 5+50) multiple (initial value : 1ah) 3 rfgain3 2 rfgain2 1 rfgain1 lsb rfgain0 downloaded from: http:///
290/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 command : &h9e meaning : resistance of center current of vco setting (initial value : 00h) bit command code meaning status msb - 6 - 5 - 4 vcoofs4 to set resistance of center current of vco. (to adjust vco offset.) on the whole, the frequency characteristic is carried up, so that the resistance is small. (31-&h9e[4:0]) ? 2.5k+2.5k [k ? ] (initial value : 00h) 3 vcoofs3 2 vcoofs2 1 vcoofs1 lsb vcoofs0 command : &h9f meaning : resistance of vco gain setting (initial value : 00h) bit command code meaning status msb - 6 - 5 - 4 - 3 vcog3 to set resistance of vco gain. the tilt of frequency characteristic. becomes step, so that the resistance is small. (15-&h9f[3:0]]) ? 5k+10k [k ? ] (initial value : 0h) 2 vcog2 1 vcog1 lsb vcog0 downloaded from: http:///
291/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 command : &ha0 meaning : ecc output data sound volume setting (initial value : 00h) (recommended value : 20h) bit command code meaning status msb - 6 - 5 eccatt1 to set sound volume from ecc output data 0 : mute (initial value) 1 : -12db 2 : 0db 4 eccatt0 3 - 2 - 1 - lsb - command : &ha1 meaning : ecc status setting and ecc test (initial value : 80h) (recommended value : 00h) bit command code meaning status msb ramclr to clear ram for ecc. be sure to set up 0 when using normal operation. 0 : normal 1 : clear (initial value) 6 cdrom cd-rom mode select. 0 : cd-da (initial value) 1 : cd-rom 5 fclr to mute against overflow of frame counter. 0 : on (initial value) 1 : off 4 selecc to select ecc correction ability. 0 : c1_2word c2_4word (initial value) 1 : c1_2word c2_2word 3 c12tst c1 series 2 word correction test. 0 : normal (initial value) 1 : test 2 - 1 - lsb - downloaded from: http:///
292/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 command : &ha4 meaning : defect and new_defect setting (initial value : 00h) bit command code meaning status msb mtnd1 to select new_defect masking time after defect. 0 : 0ms (initial value) 1 : 0.1ms 2 : 0.5ms 3 : 1.0ms 6 mtnd0 5 tnds to select the time until new_defect is set up. 0 : 19t (initial value) 1 : 35t 4 tndrs to select the time until new_defect is reset. 0 : 96t (initial value) 1 : 256t 3 wqokt to set the timing (subsyq2) to judge wqok at esp. 0 : 50% (initial value) 1 : 85% 2 ibc to set efm reconversion rom. 0 : normal (initial value) 1 : convert to 2t. 1 - lsb - command : &ha5 meaning : window and sub test setting (initial value : 00h) bit command code meaning status msb gfstst to fix gfs to h. 0 : normal (initial value) 1 : test 6 wqtst to fix wq to h. 0 : normal (initial value) 1 : test 5 lock tst to fix lock to h. 0 : normal (initial value) 1 : test 4 gfs88 tst to fix gfs88 to h. 0 : normal (initial value) 1 : test 3 ndftst to fix new_defect to l. 0 : normal (initial value) 1 : test 2 wfck tst to input wfck from mirror. 0 : normal (initial value) 1 : test 1 ssyq tst to input subsyq (2) from fok. 0 : normal (initial value) 1 : test lsb - downloaded from: http:///
293/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 command : &ha6 meaning : subq test mode (initial value : 00h) bit command code meaning status msb sqtst3 to select subq test mode. 0 : normal (initial value) other : test 6 sqtst2 5 sqtst1 4 sqtst0 3 - 2 - 1 - lsb - command : &ha8 meaning : detector of rf block setting1 (initial value : 00h) (recommended value : 98h) bit command code meaning status msb detpol to set the polarity of detect block. 0 : under eqo invert (initial value) 1 : under eqo un-invert 6 pbsbrt to select the blind time of peak/bottom short measurement sequence. 0 : 1.06 sec (initial value) 1 : 1.59 sec 5 pbsdac1 to set the width of dac increase/decrease for peak/bottom short measurement. &ha8[5:4]+1 [step] 1step=v dd ? 0.8/64 [v] (initial value : 0h) 4 pbsdac0 3 mirthl3 to set the mirror threshold level (peaklongCbottom long) ? &ha8[3:0]/16 (initial value : 0h) 2 mirthl2 1 mirthl1 lsb mirthl0 downloaded from: http:///
294/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 command : &ha9 meaning : diffect threshold level setting (initial value : 00h) (recommended value : aah) bit command code meaning status msb dsetth3 to set the threshold level of defect set side. peaklongC(&ha9[7:4] ? v dd ? 0.8/32) [v]. (initial value : 0h) 6 dsetth2 5 dsetth1 4 dsetth0 3 drstth3 to set the threshold level of defect reset side. bottomlong+(&ha9[3:0] ? v dd ? 0.8/32) [v]. (initial value : 0h) 2 drstth2 1 drstth1 lsb drstth0 command : &haa meaning : fok setting (initial value : 00h) (recommended value : 13h) bit command code meaning status msb - 6 - 5 - 4 fokd to select the method of fok judgement. 0 : decided by peak long value (initial value) 1 : decided by peak long C bottom long (amplitude) 3 fokthl3 to set the fok threshold level. at &haa[4]=0, fok is set to l by peaklong<(&haa[3:0]-8) ? v dd ? 0.8/16. at &haa[4]=1, fok is set to l by (peaklongCbottomlong)<&haa[3:0] ? v dd ? 0.8/16 (initial value : 0h) 2 fokthl2 1 fokthl1 lsb fokthl0 downloaded from: http:///
295/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 command : &hab meaning : detector of rf block setting2 (initial value : 00h) (recommended value : 03h) bit command code meaning status msb - 6 - 5 - 4 blhold to select whether to hold bottom long. 0 : dont hold (initial value) 1 : hold 3 - 2 dfctt2 to set the time of defect sequence. &hab[2:0] ? 68 sec (initial value : 0h) 1 dfctt1 lsb dfctt0 command : &hac meaning : detector of rf block setting3 (initial value : 10h) (recommended value : 00h) bit command code meaning status msb - 6 - 5 detdac test detector dac test. 0 : normal 1 : to load &ha9[5:0] 4 cmpot test of comp output. be sure to set up 0 when using normal operation. 0 : normal 1 : input from asyterminal (dfdck) (initial value) 3 fokh to fix fok to h. 0 : normal (initial value) 1 : fix to h 2 dfctl to fix defect to l. 0 : normal (initial value) 1 : fix to l 1 mirrl to fix mirror to l. 0 : normal (initial value) 1 : fix to l lsb fdmin to input fok, defect and mirror signal from external terminal. 0 : use internal signal (initial value) 1 : input from external terminal downloaded from: http:///
296/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 command : &hb3 meaning : monitor terminals i/o select (initial value : 00h) bit command code meaning status msb anam1 io to select ana_moni1 i/o. 0 : input (initial value) 1 : output 6 anam0 io to select ana_moni0 i/o. 0 : input (initial value) 1 : output 5 adm1 io to select ad_moni1 i/o. 0 : input (initial value) 1 : output 4 adm0 io to select ad_moni0 i/o. 0 : input (initial value) 1 : output 3 - 2 - 1 - lsb - command : &hb4 meaning : monitor terminals analog/digital select (initial value : 00h) bit command code meaning status msb anam1 sel to select digital/analog of ana_moni1 terminal. 0 : digital (initial value) 1 : analog 6 anam0 sel to select digital/analog of ana_moni0 terminals. 0 : digital (initial value) 1 : analog 5 adm1 sel to select digital/analog of ad_moni1 terminal. 0 : digital (initial value) 1 : analog 4 adm0 sel to select digital/analog of ad_moni0 terminal. 0 : digital (initial value) 1 : analog 3 - 2 - 1 - lsb - downloaded from: http:///
297/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 command : &hb5 meaning : on/off of pull-up resistors built in monitor terminals (initial value : 00h) bit command code meaning status msb anam1 pu to turn on/off of pull-up resistor built in ana_moni1 terminal. 0 : on (initial value) 1 : off 6 anam0 pu to turn on/off of pull-up resistor built in ana_moni0 terminal. 0 : on (initial value) 1 : off 5 adm1 pu to turn on/off of pull-up resistor built in ad_moni1 terminal. 0 : on (initial value) 1 : off 4 adm0 pu to turn on/off of pull-up resistor built in ad_moni0 terminal. 0 : on (initial value) 1 : off 3 - 2 - 1 - lsb - command : &hb6 meaning : select to universal output port (initial value : 00h) bit command code meaning status msb sm4 to set ana_moni1 terminal to universal output port. 0 : normal (initial value) 1 : output &hb7[7] content 6 sm3 to set ana_moni0 terminal to universal output port. 0 : normal (initial value) 1 : output &hb7[6] content 5 sm2 to set ad_moni1 terminal to universal output port. 0 : normal (initial value) 1 : output &hb7[5] content 4 sm1 to set ad_moni0 terminal to universal output port. 0 : normal (initial value) 1 : output &hb7[4] content 3 - 2 - 1 - lsb - downloaded from: http:///
298/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 command : &hb7 meaning : universal output register (initial value : 00h) bit command code meaning status msb tm4 to output setup value to ana_moni1 terminal. (effected at command &hb6[7]=1) 0 : outputl (initial value) 1 : outputh 6 tm3 to output setup value to ana_moni0 terminal. (effected at command &hb6[6]=1) 0 : outputl (initial value) 1 : outputh 5 tm2 to output setup value to ad_moni1 terminal. (effected at command &hb6[5]=1) 0 : outputl (initial value) 1 : outputh 4 tm1 to output setup value to ad_moni1 terminal. (effected at command &hb6[4]=1) 0 : outputl (initial value) 1 : outputh 3 - 2 - 1 - lsb - command : &hb8 meaning : select of adc for monitors (initial value : 00h) bit command code meaning status msb - 6 adc1 sel2 to select of adc for monitors. 0h : vc (initial value) 1h : ana_moni1 2h : ana_moni0 3h : ad_moni1 4h : ad_moni0 5 adc1 sel1 4 adc1 sel0 3 - 2 - 1 - lsb adc2 sel0 to select of adc for monitors2. 0 : ad_moni0 (initial value) 1 : ad_moni1 downloaded from: http:///
299/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 command : &hc0 meaning : focus on and servo test setting (initial value : 00h) (recommended value : 10h) bit command code meaning status msb - 6 - 5 fon1 to execute focus on. 0 : off (initial value) 1 : on 2 : microcomputer control (with &hc8[7:0] comand) 4 fon0 3 - 2 - 1 fdefon defect forced on/off. (to use for the test) 0 : off (initial value) 1 : on lsb fservon servo forced on/off. (to use for the test) 0 : off (initial value) 1 : on command : &hc1 meaning : tracking on and sled on (initial value : 00h) (recommended value : 11h) bit command code meaning status msb - 6 - 5 trm1 to execute tracking on. 0 : off (initial value) 1 : tracking servo on 2 : forced foward 3 : forced reverse 4 trm0 3 - 2 - 1 sdm1 to execute sled on. 0 : off (initial value) 1 : sled servo on 2 : forced foward 3 : forced reverse lsb sdm0 downloaded from: http:///
300/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 command : &hc4 meaning : execution of track jumping to the forward direction (initial value : 00h) bit command code meaning status msb tjf7 to execute track jumping to the forward direction. for the detail, refet to description of tr jump sequence. the related commands are as follows. &hcb[7:6] : to set brake pulse length per 1 track jump. &hcb[5] : to set multi-track jump mode. &hcb[4] : to set track number count signal under multi-track jump mode. &hcc[7:4] : to set blind time during track jump. &hcc[3:0] : to set over flow during track jump. &hcd[6:0] : to set long sled kick time during track jump. &hfd[7:4], [3:0] : to set track jump pulse height. in the case of &hc4[7:0]=00h, 1 track jumping is executed. (initial value) in other cases, multi-track jumping executed. when the command is &hcb[5]=0 (mode1), accelerative pulse is outputted between &hc4[7:0] tracks. when the command is &hcb[5]=1 (mode2), the jump to which accelerative pulse is outputted only between 8 tracks is repeated up to frequency which is set by &hc4[7:3]. 6 tjf6 5 tjf5 4 tjf4 3 tjf3 2 tjf2 1 tjf1 lsb tjf0 command : &hc5 meaning : execution of sled move to the forward direction (initial value : 00h) bit command code meaning status msb sjf7 to execute sled move to the forward direction. for the detail, refer to description of sled move sequence. the related commands are follows. &hcb[4] : to set track number count signal under multi-track jump mode. &hfe[7:4] : to set sled pulse height. accelerative pulse is outputted between the tracks set up by &hc5[7:0] ? 128. 6 sjf6 5 sjf5 4 sjf4 3 sjf3 2 sjf2 1 sjf1 lsb sjf0 downloaded from: http:///
301/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 command : &hc6 meaning : execution of track jumping to the reverse direction (initial value : 00h) bit command code meaning status msb tjr7 to execute track jumping to the reverse direction. for the detail, refer to description of tr jump sequence. the related commands are as follows. &hcb[7:6] : to set brake pulse length per 1 track jump. &hcb[5] : to set multi-track jump mode. &hcb[4] : to set track number count signal under multi-track jump mode. &hcc[7:4] : to set blind time during track jump. &hcc[3:0] : to set over frow during track jump. &hcd[6:0] : to set long sled kick time during track jump. &hfd[7:4],[3:0] : to set track jump pulse height. in the case of &hc6[7:0]=00h, 1 track jumping is executed. (initial value) in other cases, multi-track jumping executed. when the command is &hcb[5]=0 (mode1), decelerative pulse is outputted between &hc6[7:0] tracks. when the command is &hcb[5]=1 (mode2), the jump to which decelerative pulse is outputted only between 8 tracks is repeated up to frequency which is set by &hc6[7:3]. 6 tjr6 5 tjr5 4 tjr4 3 tjr3 2 tjr2 1 tjr1 lsb tjr0 command : &hc7 meaning : execution of sled move to the reverse direction (initial value : 00h) bit command code meaning status msb sjr7 to execution of sled move to the reverse direction. for the detail, refer to description of sled move sequence. the related commands are follows. &hcb[4] : to set track number count signal under multi-track jump mode. &hfe[7:4] : to set sled pulse height. decelerative pulse is outputted between the tracks set up by &hc7[7:0] ? 128. 6 sjr6 5 sjr5 4 sjr4 3 sjr3 2 sjr2 1 sjr1 lsb sjr0 downloaded from: http:///
302/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 command : &hc8 meaning : focus search voltage setting (initial value : 00h) (recommended value : 48h) bit command code meaning status msb fsmax3 max value of focus seach voltage (vc standard, positive side). &hc8[7:4] ? 8 ? v dd ? 0.8 / 256 [v] (initial value : 0h) 6 fsmax2 5 fsmax1 4 fsmax0 3 fsmin3 minimum value of focus search voltage (vc standard, negative side). &hc8[3:0] ? 8 ? v dd ? 0.8 / 256 [v] (initial value : 0h) 2 fsmin2 1 fsmin1 lsb fsmin0 command : &hc9 meaning : focus loop setting (initial value : 00h) (recommended value : 33h) bit command code meaning status msb fzcdm wherther to turn on the focus loop by inverted s shape. 0 : turn on (initial value) 1 : not turnon 6 fstp2 the time spent for 1-step increment of search voltage. &hc9[6:4] ? 8 ? 272 [ sec] (initial value : 0h) 5 fstp1 4 fstp0 3 - 2 fstn2 the time spent for 1-step decrement of search voltage. &hc9[2:0] ? 8 ? 272 [ sec] (initial value : 0h) 1 fstn1 lsb fstn0 downloaded from: http:///
303/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 command : &hca meaning : focus loop and recomvery (initial value : 00h) (recommended value : 26h) bit command code meaning status msb - 6 fslo2 the time until focus loop turns off after fok came to l. &hca[6:4] ? 272 [ sec] (warning)1h is prhibited (initial value : 0h) 5 fslo1 4 fslo0 3 fsrv3 focus recovery start voltage. &hca[3:0] ? 4 ? v dd ? 0.8/256 [v] (initial value : 0h) 2 fsrv2 1 fsrv1 lsb fsrv0 command : &hcb meaning : track jump setting (initial value : 00h) bit command code meaning status msb tr1w1 the output time of the inverted voltage pulse at 1 track jump. 0 : 0.5 (initial value) 1 : 0.625 2 : 0.75 3 : 1.0 6 tr1w0 5 trmm to set multi- track jump mode. 0 : mode 1 (initial value) 1 : mode 2 4 trmcs to select track number count signal in multi-track jumping. 0 : cout (initial value) 1 : tzc 3 trtzc3 to set the time to switch track number count signal to tzc in track jumping. &hcb[3:0] ? 2 ? 5.67 [ sec] (initial value : 0h) 2 trtzc2 1 trtzc1 lsb trtzc0 downloaded from: http:///
304/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 command : &hcc meaning : under track jump mode, blind time and overflow time setting (initial value : 00h) (recommended value : 36h) bit command code meaning status msb trbt3 to set blind time under track jump mode. &hcc[7:4] ? 2 ? 5.67 [ sec] (initial value : 0h) 6 trbt2 5 trbt1 4 trbt0 3 trot3 overflow time under track jump mode. &hcc[3:0] ? 2 ? 5.67 [ sec] (initial value : 0h) 2 trot2 1 trot1 lsb trot0 command : &hcd meaning : long sled kick time under track jump mode (initial value : 00h) (recommended value : 20h) bit command code meaning status msb - 6 trlst6 long sled kick time under track jump mode. &hcd[6:0] ? 272 [ sec] (initial value : 00h) 5 trlst5 4 trlst4 3 trlst3 2 trlst2 1 trlst1 lsb trlst0 downloaded from: http:///
305/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 command : &hce meaning : forced-brake, forced-gain-up and anti-shock setting (initial value : 00h) bit command code meaning status msb tjbrk forced brake on or off 0 : off (initial value) 1 : on 6 tjgup forced gain-up on or off. 0 : off (initial value) 1 : on 5 ats anti-shock mode on or off. 0 : on (initial value) 1 : off 4 sldclr whether to clear sled filter at track jumping, sled off and focus failure. 0 : clear (initial value) 1 : dont clear 3 mirrsel tracking off & lpf reset, when mirror is h. 0 : to be (initial value) 1 : not to be 2 - 1 - lsb - command : &hcf meaning : other servo setting (initial value : 00h) bit command code meaning status msb sdmode intermittent sled on/off 0 : on (initial value) 1 : off 6 sdgfsg to select sled gfs guard. 0 : on (initial value) 1 : off 5 fsvc whether to clear focus search voltage 0 : clear (initial value) 1 : dont clear 4 frcbrk whether to brake after focus recovery. 0 : dont brake (initial value) 1 : brake 3 ftr gairan foced tracking gairan on or off. 0 : off (initial value) 1 : on 2 - 1 - lsb - downloaded from: http:///
306/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 command : &hd0 meaning : various measurement for auto adjustment (initial value : 00h) bit command code meaning status msb adj3 to execute each measurement. 0h : (initial value) 1h : sdoutoffset measurement 2h : fdout offset measurement 3h : tdout offset measurement 4h : ac amplifier offset measurement 5h : bd amplifier offset measurement 6h : e amplifier offset measurement 7h : f amplifier offset measurement 8h : focus balance measurement 9h : tracking balance measurement ah : focus gain measurement bh : tracking gain measurement ch : rf measurement eh : vco measurement 6 adj2 5 adj1 4 adj0 3 - 2 - 1 - lsb - command : &hd1 meaning : sled gain measurement for auto adjustment. (initial value : 00h) bit command code meaning status msb - 6 - 5 - 4 sgadj to execute measurement of sled gain. 0 : normal (initial value) 1 : sled gain measurement 3 - 2 - 1 - lsb - downloaded from: http:///
307/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 command : &hd2 meaning : wait time for measurement for auto adjustment initial value : 00h) (recommended value : ffh) bit command code meaning status msb wait3 wait time for auto adjustment. &hd2[7:4] ? 16 ? 272 [ sec] (initial value : 0h) 6 wait2 5 wait1 4 wait0 3 adjt3 max/min measurement time. &hd2[3:0] ? 16 ? 272 [ sec] (initial value : 0h) 2 adjt2 1 adjt1 lsb adjt0 command : &hd3 meaning : tracking error cycle setting, incurred by tracking balance measurement (initial value : 00h) ) (recommended value : 38h) bit command code meaning status msb tbmin3 to set the lower limit of tracking error cycle when measurening tracking balance. &hd3[7:4] ? 8 ? 5.67 ? 2 [ sec] (initial value : 0h) 6 tbmin2 5 tbmin1 4 tbmin0 3 tbmax3 to set the upper limit of tracking error cycle when measurening tracking balance. &hd3[3:0] ? 8 ? 5.67 ? 2 [ sec] (initial value : 0h) 2 tbmax2 1 tbmax1 lsb tbmax0 downloaded from: http:///
308/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 command : &hd4 meaning : number of tracking errors until the specific requirements are met, during tracking balance measuremet. (initial value : 00h) (recommended value : 30h) bit command code meaning status msb tbn3 to set the lower limit of tracking error cycle when measuring tracking balance. &hd4[7:4] ? 8 (initial value : 0h) 6 tbn2 5 tbn1 4 tbn0 3 adjng1 to set measurement ng conditions. ng if signal selected he rein comes to l during measurement. 0 : lock (initial value) 1 : gfs88 2 : nothing 3 : nothing 2 adjng0 1 megain to select the measurement mode. (a)to set gain measurement section. (b)rfmeasurement setting. (c)balance measurement setting. (a) 0 : until disturbance down come 1 : until disturbance rise (b) 0 : disable at focus failure 1 : enable at focus failure (c) 0 : conventional method 1 : max/min measurement (&hd2[3 : 0]) lsb tdon forced tdout mode. 0 : off (initial value) 1 : on command : &hd5 meaning : read signal by &hde command selection (initial value : 00h) bit command code meaning status msb - 6 - 5 - 4 - 3 - 2 - 1 desel1 to select the read signal by &hde command. 0 : normal (max) (initial value) 1 : min 2 : (e+f)/ (ac+bd) (max) 3 : (e+f)/ (ac+bd) (min) lsb desel0 downloaded from: http:///
309/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 command : &hd6 meaning : defect,new_defect setting 1 (initial value : 00h) (recommended value : 66h) bit command code meaning status msb fdefm d1 to select focus status against defect. 0 : no countermeasure (initial value) 1 : hold 2 : gain down 6 fdefm d0 5 fnefm d1 to select focus status against new_defect. 0 : no countermeasure (initial value) 1 : hold 2 : gain down 4 fnefm d0 3 tdefm d1 to select tracking status against defect. 0 : no countermeasure (initial value) 1 : hold 2 : gain down 2 tdefm d0 1 tnefm d1 to select tracking status against new_defect. 0 : no countermeasure (initial value) 1 : hold 2 : gain down lsb tnefm d0 command : &hd7 meaning : defect,new_defect setting 2 (initial value : 00h) bit command code meaning status msb - 6 tjhsel to select hold at track jumping. 0 : bpf/through off (initial value) 1 : bpf off+through lpf 5 hsel1 to select hold against defect/new_defect. 0 : bpf/through off (initial value) 1 : bpf off+through lpf 2 : bpf/through lpf 3 : bpf off+through lpf+lpf hold 4 hsel0 3 - 2 - 1 - lsb - downloaded from: http:///
310/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 command : &hd8 meaning : servo sequencer test setting (initial value : 00h) bit command code meaning status msb - 6 - 5 sqtst5 to set servo sequencer test. 0h : normal other : test mode (initial value : 0h) 4 sqtst4 3 sqtst3 2 sqtst2 1 sqtst1 lsb sqtst0 command : &hd9 meaning : servo sequencer monitor signal select, counter test (initial value : 00h) bit command code meaning status msb - 6 sq moni2 to select servo sequencer monitor signal [7:0]. it can be read using command &hde. furthermore, the monitor signals can be output from monitor terminals by selecting status by command &hb0[7:4] and sending command &hde01. (however, at this time, the commands used for output shall be &hee00.) send &hde00 for returning to normal status. 0 : cnt2 (&hd5=0),comp_reg2 (&hd5=1) comp_reg3 (&hd5=2),comp_reg4 (&hd5=3) 1 : fsearch_cnt 2 : 00,p_reg[5:0] 3 : fhpfoff,fhpfdown,fthroff,fhpfsel,fthrsel, flpf_hold,fmuto,f_gairan_on 4 : tmuti,thpfoff,thpfdown,tthroff,thpfsel, tthrsel,tlpf_hold,tmuto 5 : t_gairan_on,smuti,sfclr,00000 6 : tj_sel[1:0],sd_sel[1:0],fzc_frd,000 5 sq moni1 4 sq moni0 3 - 2 - 1 sqc tst1 counter test of servo sequencer. 0 : normal (initial value) other : test mode lsb sqc tst0 downloaded from: http:///
311/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 command : &hde meaning : address for reading the result of measurement for auto adjustment and servo sequencer monitor signals (exclusive for reading) bit command code meaning status msb sqsta7 commands to read the result of measurement for auto adjustment which was executed by command &hd0[7:4] and &hd1[4] or moitor signals selected by command &hd9[6:4]. furthermore, the monitor signals can be output from monitor terminals by selecting status by command &hb0[7:4] and sending command &hde01. (however, at this time the commands used for output shallbe &hee00.) send &hde00 for returning to normal status. 6 sqsta6 5 sqsta5 4 sqsta4 3 sqsta3 2 sqsta2 1 sqsta1 lsb sqsta0 command : &he8 meaning : focus lpf and hpf gain setting (initial value : 00h) (recommended value : 4bh) bit command code meaning status msb flg3 to set focus lpf gain. &he8[7:4]multiple (initial value : 0h) 6 flg2 5 flg1 4 flg0 3 fhg3 to set focus hpf gain. &he8[3:0] ? 2 (initial value : 0h) 2 fhg2 1 fhg1 lsb fhg0 downloaded from: http:///
312/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 command : &he9 meaning : focus lps setting, lpf cut-off, bpf peak setting (initial value : 00h) (recommended value : 71h) bit command code meaning status msb flpsf1 to set focus lps cut-off frequency. 0 : 15.4hz (initial value) 1 : 6.7hz 2 : 3.41hz 6 flpsf0 5 flpsg1 to set focus lps attenuation level. 0 : through (initial value) 1 : ? 0.09 2 : ? 0.18 3 : ? 0.36 4 flpsg0 3 flpff1 to set focus lpf cut-off frequency. 0 : 188hz (initial value) 1 : 15.45hz 2 : 6.87hz 3 : 3.44hz 2 flpff0 1 fbpff1 to set focus bpf peak frequency. 0 : 2khz (initial value) 1 : 1khz 2 : 600hz lsb fbpff0 command : &hea meaning : tracking lpf and hpf gain setting (initial value : 00h) (recommended value : 4bh) bit command code meaning status msb tlg3 to set tracking lpf gain. &hea[7:4] multiple (initial value : 0h) 6 tlg2 5 tlg1 4 tlg0 3 thg3 to set tracking hpf gain. &hea[3:0] ? 2 multiple (initial value : 0h) 2 thg2 1 thg1 lsb thg0 downloaded from: http:///
313/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 command : &heb meaning : tracking lps setting, lpf cut-off, and bpf peak setting (initial value : 00h) (recommended value : 41h) bit command code meaning status msb tlpsf1 to set tracking lps cut-off frequency. 0 : 15.4hz (initial value) 1 : 6.7hz 2 : 3.41hz 6 tlpsf0 5 tlpsg1 to set tracking lps attenuate level. 0 : through (initial value) 1 : 0.09 2 : 0.18 3 : 0.36 4 tlpsg0 3 tlpff1 to set tracking lpf cut-off frequency. 0 : 188hz (initial value) 1 : 15.45hz 2 : 6.87hz 3 : 3.44hz 2 tlpff0 1 tbpff1 to set tracking bpf peak frequency. 0 : 2khz (initial value) 1 : 1khz 2 : 600hz lsb tbpff0 command : &hec meaning : focus, tracking gain setting (initial value : 00h) bit command code meaning status msb tgdw1 to set tracking gain-down level. 0 : 1 (initial value) 1 : 0.5 2 : 0.25 3 : 0 6 tgdw0 5 tgup1 to set tracking gain-up level. 0 : 1 (initial value) 1 : 1.5 2 : 2 3 : 3 4 tgup0 3 ftg1 to set focus total gain. 0 : 1 (initial value) 1 : 2 2 : 4 3 : 8 2 ftg0 1 ttg1 to set tracking total gain. 0 : 1 (initial value) 1 : 2 2 : 4 3 : 8 lsb ttg0 downloaded from: http:///
314/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 command : &hed meaning : disturvance setting (initial value : 00h) (recommended value : 08h) bit command code meaning status msb oscf1 to select disturbance frequency. (for measurement gain/focus balance) 0 : 1khz/500hz (initial value) 1 : 1.6khz/660hz 2 : 1.33khz/350hz 3 : 10hz (only using for tracking balance measurement) 6 oscf0 5 oscg5 to set disturbance level. &hed[5:0]/32 multiple (initial value : 00h) 4 oscg4 3 oscg3 2 oscg2 1 oscg1 lsb oscg0 command : &hee meaning : addresses for reading servo and df monitor signals (exclusive reading) bit command code meaning status msb dfsta7 commands to read signals [12:5] selected by command &hfa[7:4]. furthermore, the monitor signals [12:0] can be output from monitor terminals by selecting status by command &hb0[7:4] and sending command &hee01. (however, at this time the commands used for output shall be &hde00.) send &hee00 for returning to normal status. 6 dfsta6 5 dfsta5 4 dfsta4 3 dfsta3 2 dfsta2 1 dfsta1 lsb dfsta0 downloaded from: http:///
315/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 command : &hef meaning : servo df ram clear, ad converter input test , disturbance clear, te gain-down level,focus gain-down level, sled setting (initial value : c0h) (recommended value : 00h) bit command code meaning status msb ram clr ram clear. be sure to set up 0 when using normal operation. 0 : normal 1 : ram clear (initial value) 6 adctest ad converter input test. be sure to set up 0 when using normal operation. 0 : normal 1 : test (initial value) 5 gair clr disturbance clear. 0 : normal (initial value) 1 : disturbance clear. 4 sledf focus gain-down level. 0 : 0.5 (initial value) 1 : 0 3 tsn to select tracking servo noise shiver. 0 : off (initial value) 1 : on 2 fsn to select tracking servo noise shiver. 0 : off (initial value) 1 : on 1 pblp to set the frequency of peak/bottom long. 0 : 115hz (initial value) 1 : 230hz lsb mdac test monitor dac test. 0 : normal (initial value) 1 : &h88[7 : 0] setup value is loaded command : &hf0 meaning : intermittent sled on level setting (initial value : 00h) (recommended value : 40h) bit command code meaning status msb - 6 sth6 to set intermittent sled on level. effective when command is &hcf[7]=0. &hf0[6:0] ? v dd ? 0.8 / 256 [v] (initial value : 00h) 5 sth5 4 sth4 3 sth3 2 sth2 1 sth1 lsb sth0 downloaded from: http:///
316/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 command : &hf1 meaning : intermittent sled off level setting (initial value : 00h) (recommended value : 30h) bit command code meaning status msb - 6 stl6 to set intermittent sled off level. effective when command is &hcf[7]=0. &hf1[6:0] ? v dd ? 0.8 / 256 [v] (initial value : 00h) 5 stl5 4 stl4 3 stl3 2 stl2 1 stl1 lsb stl0 command : &hf2 meaning : fzc comparison level (initial value : 00h) (recommended value : 63h) bit command code meaning status msb fzcth3 fzc h side comparison level. &hf2[7:4] ? 8 ? v dd ? 0.8/ 256 [v] (initial value : 0h) 6 fzcth2 5 fzcth1 4 fzcth0 3 fzctl3 fzc l side comparison level. &hf2[3:0] ? 8 ? v dd ? 0.8/ 256 [v] (initial value : 0h) 2 fzctl2 1 fzctl1 lsb fzctl0 downloaded from: http:///
317/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 command : &hf3 meaning : anti-shock comparison level setting (initial value : 00h) (recommended value : 40h) bit command code meaning status msb ant lev3 to set anti-shock comparison level. &hf3[7:4] ? 2 ? v dd ? 0.8/256 [v] (initial value : 0h) 6 ant lev2 5 ant lev1 4 ant lev0 3 - 2 - 1 tlpf rimit1 to set tracking lpf rimit. 0 : nothing(initial value) 1 : 1/1 2 : 1/2 3 : 1/4 lsb tlpf rimit0 command : &hf4 meaning : sled gain setting (initial value : 00h) bit command code meaning status msb slg7 to set sled filter gain. &hf4[7:0] /4 multiple (initial value : 00h) 6 slg6 5 slg5 4 slg4 3 slg3 2 slg2 1 slg1 lsb slg0 downloaded from: http:///
318/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 command : &hf5 meaning : sled lps setting (initial value : 00h) bit command code meaning status msb - 6 - 5 - 4 - 3 - 2 slps2 to set sled filter lps. &hf5[2:0] ? (-3db) (at time of 0, it is 188hz lpf) (initial value : 0h) 1 slps1 lsb slps0 command : &hf6 meaning : fe offset, te offset setting (initial value : 00h) bit command code meaning status msb - 6 feofs2 to set fe offset. &hf6[6:4] ? v dd ? 0.8/16 [v] (initial value : 0h) 5 feofs1 4 feofs0 3 - 2 teofs2 to set te offset. &hf6[2:0] ? v dd ? 0.8/16 [v] (initial value : 0h) 1 teofs1 lsb teofs0 downloaded from: http:///
319/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 command : &hf7 meaning : tzc filter and hpf (e+f) settings (initial value : 00h) bit command code meaning status msb eafg3 to set sbad hpf (e+f) gain. &hf7[7:4]/16 multiple (initial value:0h) 6 eafg2 5 eafg1 4 eafg0 3 eaf1 to set hpf (e+f) cutoff frequency. 0 : 8khz(initial value) 1 : 4khz 2 : 2khz 2 eaf0 1 tzc1 to set tzc filter. 0 : 4.51khz (initial value) 1 : 2.12khz 2 : 0.96khz lsb tzc0 command : &hf8 meaning : ef gain-down setting (initial value : 00h) bit command code meaning status msb - 6 egdw2 e gain-down value under defect. -2 ? &hf8[6:4]db however, if &hf8[6:4]=7, gain-down value is ? 0 multiple. (initial value:0h) 5 egdw1 4 egdw0 3 - 2 fgdw2 f gain-down value under defect. -2 ? &hf8[2:0]db however, if &hf8[2:0]=7, gain-down value is ? 0 multiple. (initial value:0h) 1 fgdw1 lsb fgdw0 downloaded from: http:///
320/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 command : &hf9 meaning : te gain-down setting (initial value : 0fh) bit command code meaning status msb - 6 - 5 tegdw1 te gain down value under defect. 0 : ? 1(initial value) 1 : ? 0.5 2 : ? 0 4 tegdw0 3 tdoff3 to set tdout offset setting. add no offset at &hf9[3:0]=fh. add maximum offset at &hf9[3:0]=7h. add minimum offset at &hf9[3:0]=8h. (initial value:fh) 2 tdoff2 1 tdoff1 lsb tdoff0 command : &hfa meaning : monitor signal select (initial value : 00h) bit command code meaning status msb monisg3 to select monitor signal. 0:adc_ch2_dlaatch_out[7:0],0_0000(initial value) 1:dac_louta,dac_loutb,dac_routa,dac_routb ,000 2:servodacin[7:0],0_0000 3:adout[9:0],ad_lat[5:3] 4:adout[9:0],ad_lat[2:0] 5:moni_in,0_0000 6:peak_long,000_0000 7:botm_long,000_0000 8:clv_cnt,00 9:pp_cnt,00 a:pc_cnt,00 b:pwm_in_1d[7], to pwm_iin_1d[6:0],0_0000 c:tlpf_latch[3:0],0_0000_0000 d:audio_test_moni[7:0],0_0000 (ref. &h4f[0]) e:adc_dlat_data[9:0],000 6 monisg2 5 monisg1 4 monisg0 3 anadac 3 to select monitor sig nals form ana_moni1 and ana_moni0 terminal. ana_moni1 / ana_moni0 0 : te/fe (initial value) 1 : lpf/sled_hpf 2 : tzc/rfrp 3 : pl/bl 4 : bs/ps 5 : pl/ps 6 : bs/bl 7 : te/hpf (e+f) 8 : - / sled 2 anadac 2 1 anadac 1 lsb anadac 0 downloaded from: http:///
321/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 command : &hfb meaning : asymmetry offset setting (initial value : 80h) bit command code meaning status msb asyofs 7 to set asymmetry offset. center value 80h because of offset binary. (initial value : 80h) 6 asyofs 6 5 asyofs 5 4 asyofs 4 3 asyofs 3 2 asyofs 2 1 asyofs 1 lsb asyofs 0 command : &hfc meaning : track jump addition ratio (initial value : 80h) bit command code meaning status msb tjadd3 track jump addition ratio. &hfc[7:4]/8 multiple (initial value : 8h) 6 tjadd2 5 tjadd1 4 tjadd0 3 - 2 - 1 - lsb - downloaded from: http:///
322/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 command : &hfd meaning : tracking jump height setting (initial value : 00h) (recommended value : 44h) bit command code meaning status msb tha3 pulse height of tracking jump acceleration side (higher than vc). &hfd[7:4] ? 8 ? v dd ? 0.8 / 256 [v] (initial value : 0h) 6 tha2 5 tha1 4 tha0 3 thb3 pulse height of tracking jump deceleration side (lower than vc). &hfd[3:0] ? 8 ? v dd ? 0.8 / 256 [v] (initial value : 0h) 2 thb2 1 thb1 lsb thb0 command : &hfe meaning : sled pulse height setting (initial value : 00h) (recommended value : 80h) bit command code meaning status msb sh3 sled pulse height. &hfe[7:4] ? 8 ? v dd ? 0.8 / 256 [v] (initial value : 0h) 6 sh2 5 sh1 4 sh0 3 - 2 - 1 - lsb - downloaded from: http:///
323/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 18. general-purpose a/d converter 18.1. features successive approximation 10-bit adc analog input channels up to 8 channels supports two data output formats (straight binary and binary 2s complement) built-in power-down function analog input voltage range: 0.75 ? 0.60v (typ) conversion rate: 736 ksps (max) dnl: ? 5 lsb (max), inl: ? 5 lsb (max) 18.2. description 18.2.1. block diagram the following figure shows a block diagram of this a/d converter. figure 133. block diagram downloaded from: http:///
324/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 18.2.2. basic operation operation setting is started from apb. according to the control of the controller, the analog multiplexer selects input channels. data after a/d conversion is saved in the register (data reg) by input channel. apb reads the data after a/d conversion. 18.2.3. input channel setting the controller conducts a/d conversions by repeating t he conversion sequence from conversion slots 0 to 7. the controller conducts a single a/d conversion per one conversion slot. input channel setting for each conversion slot can be made by making register setting. figure 134 18.2.4. data output coding setting data output coding setting can be made by making register setting. this a/d converter supports two data output formats (straight binary and binary 2s complement). figure 135 and figure 136 show the theoretical transmission characteristics of the formats, respectively. figure 135. transmission characteristics of binary 2s complement (midscale: 0x000) 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 1 2 3 5 6 7 1 2 3 5 6 7 4 0 0 4 downloaded from: http:///
325/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 figure 136. transmission characteristics of straight binary 18.2.5. data output to i2s output block data of conversion slots 0 and 4 out of the eight conversion slots are outputted to the dc cut filter one after another. filtered 16-bit data are outputted to the i2s output block. figure 137. dc cut filter figure 138. data output sequence to the i2s output block downloaded from: http:///
326/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 18.3. i/o signals pin name i/o function destination pclk in apb clock clockgen presetn in apb reset (active low) resetgen psel in apb peripheral select signal apb paddr[7:0] in apb address apb pwdata[31:0] in apb write data apb pwrite in apb write signal apb penable in apb enable signal apb prdata[31:0] out apb read data apb adcdata_reb in data read request signal i2sout adcdata_hold [15:0] out add data / analog-digital data i2sout adin0 in adc analog input (0) ext i/o adin1 in adc analog input (1) ext i/o adin2 in adc analog input (2) ext i/o adin3 in adc analog input (3) ext i/o adin4 in adc analog input (4) ext i/o adin5 in adc analog input (5) ext i/o adin6 in adc analog input (6) ext i/o adin7 in adc analog input (7) ext i/o ad10clk_ir in adc core clock clockgen ad10pd_il in adc core power-down power ad10rst_il in adc core reset resetgen 18.4. register 18.4.1. memory map name description address offset width reset set_ctrl controller operation enable setting 0x00 4 0 set_ch input channel setting of each conversion slot 0x04 32 0 set_dtmd data output format setting of each conversion slot 0x08 8 0 slot0_dat data of each conversion slot after a/d conversion 0x0c 10 0 slot1_dat data of each conversion slot after a/d conversion 0x10 10 0 slot2_dat data of each conversion slot after a/d conversion 0x14 10 0 slot3_dat data of each conversion slot after a/d conversion 0x18 10 0 slot4_dat data of each conversion slot after a/d conversion 0x1c 10 0 slot5_dat data of each conversion slot after a/d conversion 0x20 10 0 slot6_dat data of each conversion slot after a/d conversion 0x24 10 0 slot7_dat data of each conversion slot after a/d conversion 0x28 10 0 downloaded from: http:///
327/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 18.4.2. register detail set_ctrl controller operation enable setting offset: 0x00 width: 4 bits bits name direction reset description 31:4 - n/a 0x0 reserved 3:2 filter_sel r/w 0x0 filter selection 0x00: dc cut filter 0x01: 4-sample mean filter 0x02: no filter 0x03 : dc cut filter +4 sample average 1 out_sel r/w 0x0 data output to the i2s output block 0: off 1: on 0 adc_ctr r/w 0x0 adc_ctr operation control 0: operation off 1: operation on set_ch input channel setting of each conversion slot offset: 0x04 width: 32 bits bits name direction reset description 31:28 set_ch7 r/w 0x0 input channel setting of conversion slot 7 27:24 set_ch6 r/w 0x0 input channel setting of conversion slot 6 23:20 set_ch5 r/w 0x0 input channel setting of conversion slot 5 19:16 set_ch4 r/w 0x0 input channel setting of conversion slot 4 15:12 set_ch3 r/w 0x0 input channel setting of conversion slot 3 11:8 set_ch2 r/w 0x0 input channel setting of conversion slot 2 7:4 set_ch1 r/w 0x0 input channel setting of conversion slot 1 3:0 set_ch0 r/w 0x0 input channel setting of conversion slot 0 set_dtmd data output format setting of each conversion slot offset: 0x08 width: 8bits bits name direction reset description 31:8 - n/a 0x0 reserved 7 set_dtmd7 r/w 0x0 data output format setting of conversion slot 7 0: binary 2s complement 1: straight binary 6 set_dtmd6 r/w 0x0 data output format setting of conversion slot 6 0: binary 2s complement 1: straight binary 5 set_dtmd5 r/w 0x0 data output format setting of conversion slot 5 0: binary 2s complement 1: straight binary 4 set_dtmd4 r/w 0x0 data output format setting of conversion slot 4 0: binary 2s complement 1: straight binary 3 set_dtmd3 r/w 0x0 data output format setting of conversion slot 3 0: binary 2s complement 1: straight binary 2 set_dtmd2 r/w 0x0 data output format setting of conversion slot 2 0: binary 2s complement 1: straight binary 1 set_dtmd1 r/w 0x0 data output format setting of conversion slot 1 0: binary 2s complement 1: straight binary 0 set_dtmd0 r/w 0x0 data output format setting of conversion slot 0 0: binary 2s complement 1: straight binary downloaded from: http:///
328/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 slotx_dat (x=0-7) data of each conversion slot after a/d conversion offset: slot0_dat - 0x0c offset: slot1_dat - 0x10 offset: slot2_dat - 0x14 offset: slot3_dat - 0x18 offset: slot4_dat - 0x1c offset: slot5_dat - 0x20 offset: slot6_dat - 0x24 offset: slot7_dat - 0x28 width: 10 bits bits direction reset description 31:10 n/a 0x0 reserved 9:0 r 0x0 data of conversion slot x (x ? 0 to 7) after a/d conversion downloaded from: http:///
329/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 19. timer 19.1. feature it has five independent programmable timers. the width of the counter of each timer is 32 bits. two count modes are supported. free orchis mode 0xffffffff is set as the counter maximum value. user setting mode the given value is set to a counter maximum value. out does the interrupt signal in each timer. the polarity of the interrupt signal is active low. little-endian 19.2. description 19.2.1. basic operation when timer counts down from the maximum value until 0, each timer generates interrupt. the width of each counter is 32 bits. as for each timer, the counter maximum value is set when timer is enabled. initial value depends on the operation mode. 19.2.2. operation mode two counter modes are supported. when the counter becomes 0, the value of the timern*loadcoun t register is loaded as a counter maximum value in the user setting mode. when the counter becomes 0, 0xffff_ff ff is loaded as a counter maximum value in the free orchis mode. 19.2.3. interrupt signal when the counter reaches initial value from 0, internal interrupt signal is generated. as for the internal interrupt signal, output is done only at one clock cycle. to set external interrupt signal (timer_intr_n), the internal interrupt signal is sent to the system clock. the external interrupt signal is generated synchronized with the system clock. the set interrupt signal is cleared by reading the timern*eoi register or the timerseoi register when it is enabled. all the interrupt signals can be cleared clearing a specific interrupt signal by reading the timern*eoi register, and reading the timerseoi register. the timing of clearing interrupts is synchronized with the system clock. the external interrupt signal is generated because the interrupt generation has higher priority than clear interrupt when timerseoi was led at the same time as generating the internal interrupt signal. when timer is enabled, the interrupt signal is cleared synchronizing with the system clock. downloaded from: http:///
330/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 19.3. i/o signals figure 139. timer module pclk presetn psel paddr[7:0] pwdata[31:0] pwrite penable prdata[31:0] scan_mode timer_en[4:0] timer_intr_n[4:0] timer_1_clk timer_2_clk timer_3_clk timer_4_clk timer_5_clk timer_1_resetn timer_2_resetn timer_3_resetn timer_4_resetn timer_5_resetn timer downloaded from: http:///
331/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 terminal list of timer module terminal name i/o description connection pclk in apb clock clockgen presetn in apb reset (active low) resetgen psel in apb peripheral selection signal apb paddr[7:0] in apb address apb pwdata[31:0] in apb write data apb pwrite in apb write signal apb penable in apb enable signal apb prdata[31:0] out apb read data apb scan_mode in scan mode setting hi: scan mode low: normal mode testdec timer_en[4:0] out timer enable signal. each timer has corresponding enable signal. the clock generator uses these signals, and the timer clock can be generated. hi: enabled state low: disabled state nc timer_intr_n[4:0] out timer interrupt signal (active low) hi: interrupt disabled low: interrupt enabled intctl timer_1_clk in clock counter of timer1 clock_gen timer_2_clk in clock counter of timer2 clock_gen timer_3_clk in clock counter of timer3 clock_gen timer_4_clk in clock counter of timer4 clock_gen timer_5_clk in clock counter of timer5 clock_gen timer_1_resetn in reset signal of timer1 reset_gen timer_2_resetn in reset signal of timer2 reset_gen timer_3_resetn in reset signal of timer3 reset_gen timer_4_resetn in reset signal of timer4 reset_gen timer_5_resetn in reset signal of timer5 reset_gen downloaded from: http:///
332/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 19.4. register 19.4.1. memory map name offset r/w width bit description timer1 load count 0x00 r/w 32 timer1 counter initial value setting register initial value: 0x0 timer1 current value 0x04 r 32 timer1 counter value initial value: 0x0 timer1 control reg 0x08 r/w 3 timer1 control register initial value: 0x0 timer1 eoi 0x0c r 1 timer1 interrupt clear register initial value: 0x0 timer1 int status 0x10 r 1 timer1 interrupt status register initial value: 0x0 timer2 load count 0x14 r/w 32 timer2 counter initial value setting register initial value: 0x0 timer2 current value 0x18 r 32 timer2 counter value initial value: 0x0 timer2 control reg 0x1c r/w 3 timer2 control register initial value: 0x0 timer2 eoi 0x20 r 1 timer2 interrupt clear register initial value: 0x0 timer2 int status 0x24 r 1 timer2 interrupt status register initial value: 0x0 timer3 load count 0x28 r/w 32 timer3 counter initial value setting register initial value: 0x0 timer3 current value 0x2c r 32 timer3 counter value initial value: 0x0 timer3 control reg 0x30 r/w 3 timer3 control register initial value: 0x0 timer3 eoi 0x34 r 1 timer3 interrupt clear register initial value: 0x0 timer3 int status 0x38 r 1 timer3 interrupt status register initial value: 0x0 timer4 load count 0x3c r/w 32 timer4 counter initial value setting register initial value: 0x0 timer4 current value 0x40 r 32 timer4 counter value initial value: 0x0 timer4 control reg 0x44 r/w 3 timer4 control register initial value: 0x0 timer4 eoi 0x48 r 1 timer4 interrupt clear register initial value: 0x0 timer4 int status 0x4c r 1 timer4 interrupt status register initial value: 0x0 timer5 load count 0x50 r/w 32 timer5 counter initial value setting register initial value: 0x0 timer5 current value 0x54 r 32 timer5 counter value initial value: 0x0 timer5 control reg 0x58 r/w 3 timer5 control register initial value: 0x0 timer5 eoi 0x5c r 1 timer5 interrupt clear register initial value: 0x0 timer5 int status 0x60 r 1 timer5 interrupt status register initial value: 0x0 timers int status 0xa0 r 5 timer module interrupt status register initial value: 0x0 timers eoi 0xa4 r 5 timer module interrupt clear register initial value: 0x0 timers raw intstatus 0xa8 r 5 timer module unmask interrupt status register initial value: 0x0 downloaded from: http:///
333/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 19.4.2. register detail timern load count timern counter initial value setting register address offset : 0x00, 0x14, 0x28, 0x3c, 0x50 reset : 0x0 bit name r/w reset description 31:0 timern load count r/w 0x0 initial value that starts the countdown of timer n is set. timern current value timern counter value register address offset : 0x04, 0x18, 0x2c, 0x40, 0x54 reset : 0x0 bit name r/w reset description 31:0 timern* current value r 0x0 cpu can read the current value of timer n. timern control reg timern control register address offset : 0x08, 0x1c, 0x30, 0x44, 0x58 reset : 0x0 bit name r/w reset description 2 r/w 0x0 interrupt / mask enable 0 : interrupt enabled 1 :mask enabled 1 r/w 0x0 timer n mode selection register 0 : free running mode 1 :user setting counter mode 0 r/w 0x0 timer n enable register counter will only work if this bit is set to 1. 0: counter disabled 1: counter enabled timern eoi timern interrupt clear register address offset : 0x0c, 0x20, 0x34, 0x48, 0x5c reset : 0x0 bit name r/w reset description 0 timern eoi r 0x0 when this register is set to 1, the interrupt of timern is cleared. timern int status timern interrupt status register address offset : 0x10, 0x24, 0x38, 0x4c, 0x60 reset : 0x0 bit name r/w reset description 0 timern int status r 0x0 timer n interrupt status register. 0 :interrupt disabled 1 :interrupt enabled timers int status timer module interrupt status register offset : 0xa0 reset : 0x0 bit name r/w reset description 4:0 timers int status r 0x0 interrupt status register even if this register is set, the interrupt signal is never cleared. the bit position corresponds to the timer number. 0 : no interrupt 1 :there is interrupt. downloaded from: http:///
334/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 timers eoi timer module interrupt clear register offset : 0xa4 reset : 0x0 bit name r/w reset description 4:0 timers eoi r 0x0 when this register is read, all timers interrupt signals are cleared. when read, it outputs 0. timers raw int status timer module unmask interrupt status offset : 0xa8 reset : 0x0 bit name r/w reset description 4:0 timers raw int status r 0x0 when this register is read, all timers interrupt signals are cleared. when read, it outputs 0. downloaded from: http:///
335/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 20. watchdog timer 20.1. feature counter value can be set, which counts every cycle. it has time-out feature. the width of the counter is 32-bits. the counter counts down from a set value. time-out occurs when counter value reaches 0. the count rate can be controlled by the clock enable pin. the time-out response can be selected from the following: system reset generation. interrupt mode. when time out occurs, interrupt is generated. once an interrupt happens due to first watchdo g timer timeout, the second timeout will generate a system reset if the first interrupt is not cleared. the time-out cycle can be set to programmable. the pulse length of system reset can be set to programmable. 20.2. description 20.2.1. counter wdt counter counts down from the set value to "0". when the counter value reaches "0", system reset or interrupt is generated depending on the selected response for time-out. response mode bit (rmod) of wdt control register controls this response. the counting continues even if system reset or interrupt is generated. when "0x76" is written in the wdt_crr register, the counter is kicked. interrupt if rmod=1 and wdt time-out occurs, interr upt is generated. if first interrupt is not cleared by the time the second interrupt arrives, system reset is generated. if the counter is reset to 0 due to kicking (writing 0x76 on wdt_crr register), no interrupt will occur. the interrupt is cleared by wdt_eoi or if kicked. shown below is the timing diagram for interrupt generation and clearing of the interrupt signal. figure 140. interrupt generation timing chart system reset if rmod=0 and wdt time-out occurs, system reset is generated. if the counter is reset to 0 due to kicking (writing 0x76 on wdt_crr register), system reset will not occur. the timing chart from the counter restart to the system reset generation is shown below. figure 141. kick-system reset timing chart 20.2.2. clock enable clock enable ( wdt_clk_en ) is done to control the count rate of the counter and it can be done from the outs ide. it is executed by the following standing up when restart during clock- enable is " low". if clock-enable is not "high", neither the interrupt nor system reset is generated. clearing the interrupt is independent of enabling the clock. 20.2.3. reset pulse length the reset pulse length is set by integral multiples of the bus clock. when system reset is generated, it remains asserted until the entire system is reset . restarting the counter after system reset is invalid. downloaded from: http:///
336/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 20.3. i/o signals figure 142. wdt module terminal list of wdt module terminal name i/o description connection pclk in apb clock clock gen presetn in apb reset (active low) reset gen psel in apb peripheral select signal apb paddr[7:0] in apb address apb pwdata[31:0] in apb write data apb pwrite in apb write signal apb penable in apb enable signal apb prdata[31:0] out apb read data apb wdt_clk_en in count up by always pclk fixed to high speed_up in this pin is used for testing. (active high). the time-out cycle becomes 256 cycles regardless of the register value. if this pin is asserted, it shortens the time for testing. time is usually fixed to low. fixed to low scan_mode in scan mode signal (active high) time is usually fixed to low. test_dec wdt_intr_n out wdt interrupt output (active low) inctl wdt_sys_rst_n out wdt system rese t output (active low) reset gen [] [] [] _ ___ __ _ wdt downloaded from: http:///
337/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 20.4. register map 20.4.1. memory map name offset r/w bit width description wdt_cr 0x00 r/w 5 control register initial value 0x12 wdt_torr 0x04 r/w 4 timeout range register initial value 0xf wdt_ccvr 0x08 r 32 current counter value register initial value 0x7fff_ffff wdt_crr 0x0c w 8 counter restart register initial value 0x0 wdt_stat 0x10 r 1 interrupt status register initial value 0x0 wdt_eoi 0x14 r 1 interrupt clear register initial value 0x0 20.4.2. register detail wdt_cr wdt control register offset: 0x00 , reset: 0x12 bit name r/w reset description 4 : 2 rpl r/w 0x4 reset pulse length setting register 0 C 2 pclk cycles 1 C 4 pclk cycles 2 C 8 pclk cycles 3 C 16 pclk cycles 4 C 32 pclk cycles 5 C 64 pclk cycles 6 C 128 pclk cycles 7 C 256 pclk cycles 1 rmod r/w 0x1 timeout response select register 0 :system reset generation 1 :system reset generation after interrupt is generated 0 wdt_en r/w 0x0 wdt enable setting if "1" is written, the watchdog timer is enabled. . "0" cannot be written when becoming effective one degree. it is nullified only by system reset. wdt_torr timeout cycle set register offset: 0x04 , reset: 0xf bit name r/w reset description 3 : 0 top r/w 0xf timeout cycle the cycle becomes 2( 16 + top ). wdt_ccvr present wdt count value reading register offset ; 0x08 , reset ; 0x7fff_ffff bit name r/w reset description 31 : 0 wdt_ ccvr r 0x7fff _ffff present wdt count value downloaded from: http:///
338/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 wdt_crr register for counter kick offset: 0x0c , reset: 0x0 bit name r/w reset description 7 : 0 wdt_ crr w 0x0 the counter is restarted by writing in this register. it becomes effective only when "0x76" is written to prevent a kick from happening by accident. wdt_stat interrupt state register offset: 0x10 , reset: 0x0 bit name r/w reset description 0 wdt_ stat r 0x0 interrupt status register of wdt 0 :there is no interrupt. 1 :there is an interrupt. wdt_eoi interrupt clear register offset: 0x14 , reset: 0x0 bit name r/w reset description 0 wdt_ eoi r 0x0 the interrupt of wdt is cleared. this is used when the clearing the interrupt without kicking the counter.. downloaded from: http:///
339/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 21. real time clock 21.1. feature 32-bit program timer increment counter the counter value can be loaded from the register setting. when the value in which the register is set matches the counter value, it generates an interrupt. the interrupt signal is active low. external crystal output is 32.768khz 21.2. description 21.2.1. clock this block uses the following clocks. bus clock pclk function part clock rtc_clk normal mode power down normal mode power down rtc system (96mhz) 32.768khz 8.192khz (32.768/4 khz) downloaded from: http:///
340/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 21.3. i/o signal figure 143. rtc module terminal list of rtc module terminal name i/o description connection pclk in apb clock clockgen present in apb reset resetgen psel in apb peripheral select signal apb paddr[4:0] in apb address apb pwdata[31:0] in apb write data apb pwrite in apb write signal apb penable in apb enable signal apb prdata[31:0] out apb read data apb scan_mode in scan mode setting hi: scan mode low: normal mode testdec rtc_clk in realtime clock counter clockgen rtc_rst_n in reset of real time clock counter resetgen rtc_intr_n out interrupt signal (active low) ictl rtc_en out free rank lock demand signal open 21.4. register 21.4.1. memory map name description address offset r/w width reset rtc_ccvr current counter value register 0x00 r 32bit 0x0 rtc_cmr counter match register 0x04 r/w 32bit 0x0 rtc_clr counter load register 0x08 r/w 32bit 0x0 rtc_ccr counter control register 0x0c r/w 4bit 0x0 rtc_stat interrupt status register 0x10 r 32bit 0x0 rtc_rstat interrupt raw status register 0x14 r 32bit 0x0 rtc_eoi end of interrupt register 0x18 r 32bit 0x0 rtc_comp_version component version register 0x1c r 32bit 0x3230332a pclk presetn psel paddr[4:0] pwdata[31:0] pwrite penable prdata[31:0] scan_mode rtc_intr_n rtc_clk rtc_rst_n rtc_en rtc downloaded from: http:///
341/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 21.4.2. register details current counter value register the current value of an internal counter address offset : 0x00 bits name direction reset description 31:0 current counter value r 0x0 current value of internal counter counter match register the interrupt match register address offset : 0x04 bits name direction reset description 31:0 counter match r/w 0x0 when the internal counter matches the value of the corresponding register, interrupt is generated. counter load register the counter loading register address offset : 0x08 bits name direction reset description 31:0 counter load r/w 0x0 value of this register is loaded into the counter counter control register the counter control register address offset : 0x0c bits name direction reset description 3 rtc_wen r/w 0x0 when the match is generated instead of doing weight until the counter reaches the maximum value, the counter is wrapped. 0 = wrap disabled 1 = wrap enabled 2 rtc_en r/w 0x0 the counter is controlled. 0 = counter disabled 1 = counter enabled 1 rtc_mask r/w 0x0 mask of interrupt 0: the mask is not done. 1: the mask is done. 0 rtc_ien r/w 0x0 interrupt generation permission 0: interrupt is not possible. 1: interrupt is possible. interrupt status register the interrupt status register address offset : 0x10 bits name direction reset description 31:1 n/a n/a - reserved 0 rtc_stat r 0x0 the register that does masking for interrupt status 0: interrupt is not active 1: interrupt is active interrupt raw status register interrupt raw status register address offset : 0x14 bits name direction reset description 31:1 n/a n/a - reserved 0 rtc_rstat r 0x0 the interrupt status register that doesn't do the mask 0: interrupt is not active 1: interrupt is active downloaded from: http:///
342/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 end of interrupt register an interrupt clear register address offset : 0x18 bits name direction reset description 31:1 n/a n/a - reserved 0 rtc_eoi r 0x0 when this register is set, the match interrupt is cleared. component version register component version address offset : 0x1c bits name direction reset description 31:0 rtc_comp_versio n r 0x3230332a rtc module version management number downloaded from: http:///
343/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 22. remote controller receiver (rcr) 22.1. features converts infrared remote control signal into code supports the aeha communication format generates interrupts (leader signal, data signal, end-of-frame, and data error detection interrupts) supports inversion of input signal polarity has built-in de-noising circuit allows h/l signal width setting 22.2. description 22.2.1. block diagram the following figure shows the block diagram of this remote control receiver. figure 144. block diagram 22.2.2. aeha communication format the following section shows the waveform of the aeha communication format that this rcr supports. 1t: 350 to 500us (typ: 425us) figure 145. aeha communication format (for one frame) noise filter downloaded from: http:///
344/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 22.2.3. basic operation set the register rcr_on=1after completion of the settings for input signal polarity, denoising width, end-of-frame count, interrupt mask, and h-l signal. thecomparison starts the signal counting and code conversion. when a leader signal, data signal, or end-of frame is detected, an interrupt signal is generated and receive data register values are rewritten. after completion of data readout, clear the interrupt. if an error is detected during data readout, a data error detection interrupt is generated. if a data error is detected, ignore data on the relevant frame. example for acquisition of leader + 33-bit data (when 1t ? 425us) figure 146. 22.2.4. operational clock the following table shows the operational clock of the rcr block. the clock operates at a frequency of 32.768 khz at all times. 22.2.5. inversion of input signal polarity the rcr inverts the polarity of an input signal, and then proceeds with subsequent processing. 22.2.6. noise filter if a sampled signal level is maintained for the number of sampling times set with the register rcr_set, the noise filter imports the said level. signals that did not maintain the level for the set number of sampling times are ignored. 22.2.7. pulse width measurement counter this counter is used to make measurement of pulse width. w hen the rising or falling edge of input signal is detected, the counter increments the pulse width until the s ubsequent rising or falling edge is detected. furthermore, this counter is also used to determine the end of frame and cleared at the end of frame. 22.2.8. interrupts leader signal detection interrupt: it is generated when the leader signal is detected. the detection is judged according to the set value of rcr_set_l. data signal detection interrupt: it is generated when data of 32 bits are detected. end-of-frame detection interrupt: it is generated when the va lue of the pulse with measurement counter reaches the set value of the register rcr_set. the counter is cleared at the same time. data error detection interrupt: it is generated when h/l width in the data section (1t or 3t) is not consistent with t he set value of rcr_set_d0/1. function apb i/f standby mode 32.768 khz 32.768 khz normal mode 32.768 khz system clock leader signal detection interrupt deta signal detection interrupt frame detection interrupt leader signal detection interrupt downloaded from: http:///
345/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 22.2.9. received data data signal after 0/1 judgment is saved in the 0th bit of the temporary storage register. when the subsequent data is received, the saved data is shifted to upper bit in steps of 1 bit and new data is inputted in the 0th bit. when data of 32 bits are received, the data are saved in the received data retention register (rcr_data) and the temporary storage register is cleared. at the end of frame, the temporary storage register value at the time is saved in rcr_data. since the register rcr_data_v is incremented by 1 every time it receives data after 0/1 judgment, the number of significant bits of data is indicated. ensure the number of effective bits at the same time when reading data. 22.2.10. handling of error signal if the length of leader signal is out of the set value of the register rcr_set_l: unless the leader signal is normally detected, the data is not decoded. as a result, the value of the register rcr_data is not updated. furthermore, no detection interrupt is generated. if the leader signal is not detected, but the data signal is only detected: unless the leader signal is normally detected, data is not decoded. as a result, the value of the register rcr_data is also not updated. furthermore, no detection interrupt is generated. if the leader signal is normally detected, but the length of the data signal is out of the set value of the register rcr_set_d0/1: since the leader signal was detected, the data is decoded. when any data error is detected, a data error detection interrupt is generated. even if the data error occurs, the value of the register rcr_data is updated when data of 32 bits are received or the end of frame is detected. as a result, data that can be read in this case becomes incorrect data. data on the frame in which the data error was detected should be ignored. if the subsequent frame is received in a period of time shorte r than that to be taken for the judgment of the end of frame (rcr_set [15:4]): if any signal change is made in a period of time shorter than that to be taken for the judgment of the end of frame, it is determined that data error has been detected, resulting in the generation of data error detection interrupt. in this case, handle the error in the same manner as that to be taken when a normal data error is detected. 22.3. i/o signals pin name i/o function destination pclk_i in apb clock clockgen present in apb reset (active low) resetgen psel in apb peripheral select signal apb paddr [15:0] in apb address apb pwdata [31:0] in apb write data apb pwrite in apb write signal apb penable in apb enable signal apb prdata [31:0] out apb read data apb pclk_fun_i in rcr function clock (32.768 khz) clockgen rcrdata_org in rcr data input pad rcr_irq_o out interrupt request signal ictl downloaded from: http:///
346/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 22.4. register 22.4.1. memory map name description address offset width reset rcr_on rcr operation enable setting 0x00 1 0x0 rcr_set input signal processing setting 0x04 4 0x4 rcr_set_l leader section setting 0x08 32 0x0 rcr_set_d0 data 0 section setting 0x0c 32 0x0 rcr_set_d1 data 1 section setting 0x10 16 0x0 rcr_data received data 0x14 32 0x0 rcr_data_v number of significant bits of received data 0x18 6 0x0 rcr_irq interrupt 0x1c 4 0x0 rcr_irq_cl interrupt clear 0x20 4 0x0 rcr_irq_msk mask for cause of interrupt 0x24 4 0xf 22.4.2. register detail rcr_on rcr operation enable setting offset: 0x00 width: 1 bit bits name direction reset description 0 rcr_on r/w 0x0 rcr operation control setting 1 to this bit after completion of setting of registers rcr_set, rcr_set_l, rcr_set_d0, and rcr_set_d1 starts the rcr operation. 0: operation off 1: operation on rcr_set input signal processing setting offset: 0x04 width: 4 bits bits name direction reset description 15:4 set_end 0x0 end-of-frame judgment count setting sets the length of section in which no bit changes are made to judge the end of frame judgment time ? (1 ? 32 .768khz) ? set value max: 125 ms (set value: 0xfff) 3:1 set_fltr r/w 0x2 denoising width setting 0: reserved 1: 30.5 us 2: 61.0 us 3: 91.5 us 4: 122 us 5: 153 us 6: 183 us 7: 214 us 0 set_inv r/w 0x0 input signal polarity setting 0: normal, 1: inversed downloaded from: http:///
347/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 rcr_set_l leader section setting offset: 0x08 width: 32 bits bits name direction reset description 31:24 set_ldh_max r/w 0x0 maximum count setting in the h section of leader signal set this register so that min will be equal to or smaller than max. (max.: 7.781ms, 1t equivalent: 972us) 23:16 set_ldh_min r/w 0x0 minimum count setting in the h section of leader signal 15:8 set_ldl_max r/w 0x0 maximum count setting in the l section of leader signal set this register so that min will be equal to or smaller than max. 7:0 set_ldl_min r/w 0x0 minimum count setting in the l section of leader signal rcr_set_d0 data section setting offset: 0x0c width: 32 bits bits name direction reset description 31:24 set_dth_max r/w 0x0 maximum count setting in the h section when data ? 0/1 set this register so that min will be equal to or smaller than max. 23:16 set_dth_min r/w 0x0 minimum count setting in the h section when data ? 0/1 15:8 set_dtl_max r/w 0x0 maximum count setting in the l section when data ? 0 set this register so that min will be equal to or smaller than max. 7:0 set_dtl_min r/w 0x0 minimum count setting in the l section when data ? 0 rcr_set_d1 data section setting offset: 0x10 width: 32 bits bits name direction reset description 15:8 set_dtl_max r/w 0x0 maximum count setting in the l section when data ? 1 set this register so that min will be equal to or smaller than max. 7:0 set_dtl_min r/w 0x0 minimum count setting in the l section when data ? 1 rcr_data received data offset: 0x14 width: 32 bits bits name direction reset description 31:0 rcv_data r/w 0x0 32-bit received data rcr_data_v number of significant bits of received data offset: 0x18 width: 6 bits bits name direction reset description 5:0 varid_bit r/w 0x0 number of significant bits downloaded from: http:///
348/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 rcr_irq interrupt offset: 0x1c width: 4 bits bits name direction reset description 3 irq_dat r 0x0 data error detection interrupt 0: no interrupt generated 1: interrupt generated 2 irq_frm r 0x0 end of frame detection interrupt 0: no interrupt generated 1: interrupt generated 1 irq_dat r 0x0 data signal detection interrupt 0: no interrupt generated 1: interrupt generated 0 irq_ldr r 0x0 leader signal detection interrupt 0: no interrupt generated 1: interrupt generated rcr_irq_cl interrupt clear offset: 0x20 width: 4 bits bits name direction reset description 3 rcr_irq_cl[3] r/w 0x0 data error detection interrupt clear 1: interrupt cleared 2 rcr_irq_cl[2] r/w 0x0 end of frame detection interrupt clear 1: interrupt cleared 1 rcr_irq_cl[1] r/w 0x0 data signal detection interrupt clear 1: interrupt cleared 0 rcr_irq_cl[0] r/w 0x0 leader signal detection interrupt clear 1: interrupt cleared rcr_irq_msk mask for cause of interrupt offset: 0x24 width: 4 bits bits name direction reset description 3 rcr_irq_msk[3] r/w 0x1 data error detection interrupt mask 0: unmasked, 1: masked 2 rcr_irq_msk[2] r/w 0x1 end of frame detection interrupt mask 0: unmasked, 1: masked 1 rcr_irq_msk[1] r/w 0x1 data signal detection interrupt mask 0: unmasked, 1: masked 0 rcr_irq_msk[0] r/w 0x1 leader signal detection interrupt mask 0: unmasked, 1: masked downloaded from: http:///
349/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 23. clock generator 23.1. features designed to supply clo cks to internal blocks allows the on/off control of clocks for the blocks generates an audio master clock supports power-down mode 23.2. description 23.2.1. block diagram the following figure shows the clkgen controller block diagram. _ _ _ figure 147. clkgen controller block diagram 23.2.2. input control block this block selects between pll or test clock for clock input to blocks. 23.2.3. clkdiv2_div32 and clkdiv2_4 blocks these blocks are used to divide pll clock frequency from 2 to 32. pll clock frequency for audio is divided by 2, 4, 3, and 6. 23.2.4. syssel block this block is used to shift to system clock set with software. the system clock is selectable according to normal mode (96 mhz) or power-down mode (32 khz). downloaded from: http:///
350/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 23.2.5. clksel block this block is used to enable or disable clocks to individual blocks according to clock enab le signal set with software. 23.2.6. clock control signal generator this block is used to generate clock control signals set with software. this signal generator allows selecti ng of system clock to operate arm9 to normal mode (96 mhz) and power-down mode (32 khz) accordingly. the signal generator also allows the following settings: - frequency dividing setting by clock to be supplied to each clock - clock supply stop/start setting by clock to be supplied to each block - analog block stop/start setting - oscillation circuit stop/start setting 23.2.7. power-down mode for power management, normal mode and power-down mode for power saving are provided. normal mode: the system clock operates at a frequency of 96 mhz. power-down mode: the system clock operates at a frequency of 32.768 khz inputted from subxin. switching between normal mode and power-down mode is enabled by software register setting. by switching to power-down mode, input clocks to unnecessary blocks are disabled. thus, power consumption is reduced. 23.2.8. clocks in logic block the following table lists clocks in the logic block. bus clock clock in function block block normal mode power-down mode normal mode mhz power-down mode arm9 - - system 96 32.768k amba system 32.768k - 96 - serial flash i/f system 32. 768k sfr 73.728 32.768k - - sfr 73.728 (inverted) 32.768k (inverted) wdt system 32.768k - - - timer1 system 32.768k system (note 1) 96 32.768k timer2 - - system (note 1) 96 32.768k timer3 - - system (note 1) 96 32.768k timer4 - - system (note 1) 96 32.768k timer5 - - system (note 1) 96 32.768k clock controller system 32.768k - - - pin controller system 32.768k - - - rtc system 32.768k rtc 8.192k 8.192k uart0 system 32.768k system (note 1) 96 32.768k uart1 system 32.768k system (note 1) 96 32.768k spi0 system 32.768k system (note 1) 96 32.768k spi1 system 32.768k system (note 1) 96 32.768k i2c0 system 32.768k system (note 1) 96 32.768k i2c1 system 32.768k system v 96 32.768k i2s output system 32.768k audio audio 32.768k downloaded from: http:///
351/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 clocks in logic blocks C continued bus clock clock in function block cd-dsp system 32.768k xin 16.9344 32.768k adc system 32.768k xin 16.9344 32.768k remap system 32.768k - - - rcr system 32.768k rcr 32.768k 32.768k gpio0 system 32.768k system (note 1) 96 32.768k gpio1 system 32.768k system (note 1) 96 32.768k dmac system 32.768k - - - i2sin/cd-rom system 32.768k system (note 1) 96 32.768k sdio i/f system 32.768k system 96 32.768k usb controller system 32. 768k usb 60 32.768k usb connect detector system 32.768k system 32.768k 32.768k usb phy - - phy 12m 32.768k ictl system 32.768k - - - (note 1) available for selection of frequency-dividing clock 23.2.9. sdram clocks block signal name normal mode mhz power-down mode sdram controller: used for bus and controller sdrc_hclk_o system 96 32.768 khz sdram controller: used for writepipe sdrc_hclkb_o used to invert sdrc_hclk_o clock for output to sdram osdram_clk_o used for delay selection and output of sdrc_hclk_o clock for capture from sdram isdram_clk_o used for delay selection and output of isdram_clk_i 23.2.10. audio clocks the following clocks are supplied as audio output clocks. sampling frequency 256 fs 96 fs unit 192 khz (48-khz system) 49.152 - mhz 176.4 khz (44.1-khz system) 45.1584 16.9344 mhz downloaded from: http:///
352/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 23.3. i/o signals pin name i/o function destination sys_clk_i in apb bus clock clkctr rstb_i in reset (active low) rstgen paddr_i in apb bus address apb penable_i in apb bus enable apb pwdata_i in apb bus write data apb pwrite_i in apb bus write enable apb psel_i in apb bus selector apb prdata _o out apb bus read data apb xinmain_clk_i in xin clock input pad xinsub_clk_i in sub clock input pad pllsys_clk_i in pll(system) clock input pll pllaud1_clk_i in pll(audio) clock input pll pllaud2_clk_i in pll(audio) clock input pll pllusb_clk_i in pll(usb) clock input pll isdram_clk_i in clock for capture from sdram return clock for pad_***.cin pad sys_clk_o out system clock logic phy12m_clk_o out usb-phy 12m clock usb-phy usbx_clk_o out usb 60m clock usb wdt_clk_o out wdt clock logic tm1_clk_o out timer1 clock logic tm2_clk_o out timer2 clock logic tm3_clk_o out timer3 clock logic tm4_clk_o out timer4 clock logic tm5_clk_o out timer5 clock logic rtc_clk_o out rtc clock logic uart0_clk_o out uart clock logic uart1_clk_o out uart clock logic spi0_clk_o out spi1 clock logic spi1_clk_o out spi2 clock logic i2c0_clk_o out i2c1 clock logic i2c1_clk_o out i2c2 clock logic gpio_clk_o out gpio clock logic dmac_clk_o out dmac clock logic pdm_clk_o out peri dmac clock logic cdr_clk_o out cd-rom clock logic sdrc_hclk_o out sdram controller: used for bus and controller logic sdrc_hclkb_o out sdram controller: used for writepipe logic qspi_clk_o out quad-spi clock logic sdio_clk_o out sdio clock logic downloaded from: http:///
353/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 i/o signals C continued 23.4. register 23.4.1. memory map name description address offset width reset clk_ctl0 system clock control 0x00 32 32h00000000 clk_ctl1 clock divider control 0x04 32 32h00000000 clk_ctl2 clock divider control 0x08 32 32h00000000 clk_ctl3 clock divider control 0x0c 32 32h00000000 clk_ctl5 clock enable control 0x14 32 32h00000000 clk_ctl6 clock enable control 0x18 32 32h00000000 clk_ctl7 clock enable control 0x1c 32 32h00000000 clk_ctl8 clock enable control 0x20 32 32h00000000 sdram_incl k_delay sdram in clock delay register 0x24 8 16h0000 sdram_out clk_ delay sdram out clock delay register 0x28 8 16h0000 pin name i/o function destination usbd_clk_o out usb dma clock logic sdw_clk_o out shadow clock logic sfr_clk_o out serial flach clock logic sdr_clk_o out sd-ram clock logic aud1_clk_o out audio clock (45.1584mhz) logic aud2_clk_o out audio clock (33.8688mhz) open aud3_clk_o out audio clock (49.152mhz) logic aud4_clk_o out audio clock (36.864mhz) open aud5_clk_o out audio clock (16.9344mhz) logic cdd_clk_o out cd-dsp clock logic adc_clk_o out adc clock logic osdram_clk_o out clock for output to sd-ram logic isdram_clk_o out clock for capture from sd-ram logic downloaded from: http:///
354/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 23.4.2. register detail clk_set0 offset: 0x00 width: 32 bits bits name direction reset description 15 r/w 0x0 - 14 r/w 0x0 - 13 r/w 0x0 - 12 r/w 0x0 selects operation mode of cd (analog) 0: power on 1: power off 11 r/w 0x0 selects operation mode of adc 0: power on 1: power off 10 r/w 0x0 selects operation mode of pll audio2 0: power on 1: power off 9 r/w 0x0 selects operation mode of pll audio1 0: power on 1: power off 8 r/w 0x0 selects operation mode of pll system 0: power on 1: power off 7:6 r/w 0x0 - 5 r/w 0x0 - 4 r/w 0x0 selects operation mode of oscillation circuit for main clock input 0: start operation 1: stop operation 3:1 r/w 0x0 - 0 r/w 0x0 selects system clock (arm9 operation clock) 0: 96 mhz 1: 32 khz (power-down) downloaded from: http:///
355/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 clk_set1 offset: 0x04 width: 32 bits bits name direction reset description 31:28 r/w 0x0 gpio1 settings (gpio clock) 4h0: system clock / 1/1 frequency-divided 4h1: system clock / 1/2 frequency-divided 4h2: system clock / 1/4 frequency-divided 4h3: system clock / 1/8 frequency-divided 27:24 r/w 0x0 gpio0 settings (gpio clock) 4h0: system clock / 1/1 frequency-divided 4h1: system clock / 1/2 frequency-divided 4h2: system clock / 1/4 frequency-divided 4h3: system clock / 1/8 frequency-divided 23:20 r/w 0x0 tim5 settings (timer5 clock) 4h0: system clock / 1/1 frequency-divided 4h1: system clock / 1/2 frequency-divided 4h2: system clock / 1/4 frequency-divided 4h3: system clock / 1/8 frequency-divided 19:16 r/w 0x0 tim4 settings (timer4 clock) 4h0: system clock / 1/1 frequency-divided 4h1: system clock / 1/2 frequency-divided 4h2: system clock / 1/4 frequency-divided 4h3: system clock / 1/8 frequency-divided 15:12 r/w 0x0 tim3 settings (timer3 clock) 4h0: system clock / 1/1 frequency-divided 4h1: system clock / 1/2 frequency-divided 4h2: system clock / 1/4 frequency-divided 4h3: system clock / 1/8 frequency-divided 11:8 r/w 0x0 tim2 settings (timer2 clock) 4h0: system clock / 1/1 frequency-divided 4h1: system clock / 1/2 frequency-divided 4h2: system clock / 1/4 frequency-divided 4h3: system clock / 1/8 frequency-divided 7:4 r/w 0x0 tim1 settings (timer1 clock) 4h0: system clock / 1/1 frequency-divided 4h1: system clock / 1/2 frequency-divided 4h2: system clock / 1/4 frequency-divided 4h3: system clock / 1/8 frequency-divided 3:0 r/w 0x0 - downloaded from: http:///
356/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 clk_set2 offset: 0x08 width: 32 bits bits name direction reset description 31:28 r/w 0x0 - 27:24 r/w 0x0 - 23:20 r/w 0x0 i2c1 settings (i2c clock) 4h0: system clock / 1/1 frequency-divided 4h1: system clock / 1/2 frequency-divided 4h2: system clock / 1/4 frequency-divided 4h3: system clock / 1/8 frequency-divided 19:16 r/w 0x0 i2c0 settings (i2c clock) 4h0: system clock / 1/1 frequency-divided 4h1: system clock / 1/2 frequency-divided 4h2: system clock / 1/4 frequency-divided 4h3: system clock / 1/8 frequency-divided 15:12 r/w 0x0 spi1 settings (spi1 clock) 4h0: system clock / 1/1 frequency-divided 4h1: system clock / 1/2 frequency-divided 4h2: system clock / 1/4 frequency-divided 4h3: system clock / 1/8 frequency-divided 11:8 r/w 0x0 spi0 settings (spi0 clock) 4h0: system clock / 1/1 frequency-divided 4h1: system clock / 1/2 frequency-divided 4h2: system clock / 1/4 frequency-divided 4h3: system clock / 1/8 frequency-divided 7:4 r/w 0x0 uart1 settings (uart1 clock) 4h0: system clock / 1/1 frequency-divided 4h1: system clock / 1/2 frequency-divided 4h2: system clock / 1/4 frequency-divided 4h3: system clock / 1/8 frequency-divided 3:0 r/w 0x0 uart0 settings (uart0 clock) 4h0: system clock / 1/1 frequency-divided 4h1: system clock / 1/2 frequency-divided 4h2: system clock / 1/4 frequency-divided 4h3: system clock / 1/8 frequency-divided downloaded from: http:///
357/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 clk_set3 offset: 0x0c width: 32 bits bits name direction reset description 31:24 r/w 0x0 - 23:20 r/w 0x0 sdio settings (sdio clock) 4h0: system clock / 1/1 frequency-divided 4h1: system clock / 1/2 frequency-divided 4h2: system clock / 1/4 frequency-divided 4h3: system clock / 1/8 frequency-divided 19:16 r/w 0x0 sfrom settings (serial flash rom clock) 4h0 : 73.73 mhz inverted 4h1: system clock / 1/2 frequency-divided 4h2: system clock / 1/4 frequency-divided 4h3: system clock / 1/8 frequency-divided 15:12 r/w 0x0 - 11:8 r/w 0x0 cd-rom settings (cd-rom clock). 4h0: system clock / 1/1 frequency-divided 4h1: system clock / 1/2 frequency-divided 4h2: system clock / 1/4 frequency-divided 4h3: system clock / 1/8 frequency-divided 7:0 r/w 0x0 - downloaded from: http:///
358/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 clk_set5 offset: 0x14 width: 32 bits bits name direction reset description 31:0 r/w 0x0 enables or disables clock supply to each function block 1b0: clock supply in progress 1b1: clock supply stopped refer to the table shown below for correspondence between bits and blocks. bit block 0 - 1 sd-ram i/f 2 - 3 timer1 4 timer2 5 timer3 6 timer4 7 timer5 8 - 9 - 10 uart0 11 uart1 12 spi0 13 spi1 14 i2c0 15 i2c1 16 - 17 gpio0 18 gpio1 19 - 20 - 21 cd-rom 22 sdram controller sdrc_hclkb_o 23 serial flash i/f inverted 24 sdio i/f 25 usb connect detector 26 - downloaded from: http:///
359/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 clk_set6 offset: 0x18 width: 32 bits bits name direction reset description 31:0 r/w 0x0 enables or disables clock supply to each function block 1b0: clock supply in progress 1b1: clock supply stopped refer to the table shown below for correspondence between bits and blocks. bit block 0 serial flash i/f 1 rtc 2 i2s output - 45.1584 mhz 3 - 4 i2s output - 49.152 mhz 5 - 6 i2s output - 16.9344 mhz 7 cd-dsp 8 adc 9 rcr 10 - 11 usb controller 12 usb phy downloaded from: http:///
360/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 clk_set7 offset: 0x1c width: 32 bits bits name direction reset description 31:0 r/w 0x0 enables or disables clock supply to the amba bus of each block 1b0: clock supply in progress 1b1: clock supply stopped refer to the table shown below for correspondence between bits and blocks. bit bus block 0 - 1 sd-ram i/f 2 wdt 3 timer1-5 4-7 - 8 clock controller 9 pin controller 10 uart0 11 uart1 12 spi0 13 spi1 14 i2c0 15 i2c1 16 remap 17 gpio0 18 gpio1 19 dmac 20 - 21 cd-rom 22 sdram controller sdrc_hclk_o 23 - 24 sdio i/f 25 usb connect detector 26 ictl clocks of wdt, dmac, sd-ram controller, and ictl function blocks are shared with the amba bus. consequently, when stopping the clock supply to the amba bus, the clock inputs to the function blocks are also stopped. downloaded from: http:///
361/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 clk_set8 offset: 0x20 width: 32 bits bits name direction reset description 31:0 r/w 0x0 enables or disables clock supply to the amba bus of each function block 1b0: clock supply in progress 1b1: clock supply stopped refer to the table shown below for correspondence between bits and blocks. bit bus block 0 serial flash i/f 1 rtc 2 i2s output 3-6 - 7 cd-dsp 8 adc 9 rcr 10 - 11 usb controller 12 usb phy sdram_inclk_delay offset: 0x24 width: 8 bits bits name direction reset description 7:0 - r/w 0x0 selects the clock to be used in capturing data inputted from sdram (selects delay time to input clock returned from pad.cin) when [7] is set to 1, clock is inverted. when [7] is set to 0, a value from 0 to 20 is set. please use this bit with a reset value. sdram_outclk _delay offset: 0x28 width: 8 bits bits name direction reset description 7:0 - r/w 0x0 selects the clock to be used in outputting data to sdram (selects delay time to output data from system clock) when [7] is set to 1, clock is inverted. when [7] is set to 0, a value from 0 to 20 is set. please use this bit with a reset value. downloaded from: http:///
362/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 24. reset generator 24.1. features designed to generate reset si gnals to be supplied to blocks has a built-in circuit used to denoise the reset signals has a built-in timer used to reset the system 24.2. description 24.2.1. outline circuit diagram figure 148. rstgen module 24.2.2. description 24.2.3. timing chart figure 149. downloaded from: http:///
363/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 24.2.4. denoising circuit for denoising reset signals, input a reset signal in a 9-bit shift register and use or for output. 32.768-khz clock is used for denoising. consequently, reset input to pad should be held at least for a period of 300 us in order to detect the reset signal. 24.2.5. system reset counter internal system reset signal is maintained at the l level for a period of 7.78 ms after denoised reset signal reaches the h level. 24.2.6. phy reset counter phy reset signal in the usb block and a signal to suspendm are outputted as shown in the above timing chart. 24.2.7. wdt reset connecting reset output signal from wdt block directly to the reset pin of the wdt block via the reset generator will stop wdt output operation in progress. as a result, a reset signal due to wdt timeout is not outputted to the wdt block itself. the wdt block is reset independently by inputting a signal from pad or making register setting. downloaded from: http:///
364/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 24.3. i/o signals pin name i/o function destination clk_i in clock (32.768 khz) clkgen sys_clk_i in internal system clock clkgen asyrstb_i in reset (active low from pin) pad tmode_i in tmode pin pad wdtrstb_i in reset (active low from wdt) wdt paddr in apb address apb pwdata in apb write data apb pwrite in apb write enable apb penable in apb w/r enable apb psel in apb slave select apb pdata out apb data out apb syn_rstb_o out internal system reset output arm,amba wdt_rstn_o out reset to wdt wdt timer1_rstn_o out timer1-5 reset output timer clkgen_rstn_o out clkgen reset output clkgen pinctrl_rstn_o out pin controller reset output pin controller rtc_rstn_o out rtc reset output rtc uart0_rstn_o out uart0 reset output uart0 uart1_rstn_o out uart1 reset output uart1 spi0_rstn_o out spi0 reset output spi0 spi1_rstn_o out spi1 reset output spi1 i2c0_rstn_o out i2c0 reset output i2c0 i2c1_rstn_o out i2c1 reset output i2c1 i2sout_rstn_o out i2s output reset output i2s output cdd_rstn_o out cd dsp reset output cd dsp adc_rstn_o out adc reset output adc remap_rstn_o out remap reset output remap rcr_rstn_o rcr reset output rcr gpio0_rstn_o out gpio0 reset output gpio0 gpio1_rstn_o out gpio1 reset output gpio1 dmac_rstn_o out dmac reset output dmac cdr_rstn_o out cd-rom reset output cd-rom sdrc_rstn_o out sdram controller reset output sdram controller qspi_rstn_o out quad spi reset output open sdio_rstn_o out sdio reset output sdio sdw_rstn_o out shadow ram reset output open sfl_rstn_o out serial flash reset output serial flash sdr_rstn_o out sdram reset output open usbd_rstn_o out usb reset output usb usbc_rstn_o out usb controller reset output usb controller usbphy_rst_o out usb phy reset output usb phy usb_suspendm_o out usb suspend (3.89 ms ount) usb phy 24.4. register 24.4.1. memory map name description address offset width reset softrst_ctrl0 software reset control 0x00 32bit 0x0 softrst_ctrl1 software reset control 0x04 32bit 0x0 downloaded from: http:///
365/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 24.4.2. register detail softrst_ctrl0 this register is used to make software reset setting. offset: 0x00 softrst_ctrl1 this register is used to make software reset setting. offset: 0x04 bits name direction reset description 0 wdt_rst r/w 0 wdt block 0: reset cleared (normal operation) 1: reset set the sample bit logic applies to the following reset setting. 1 timer1_rst r/w 0 timer1 to 5 2-5 - r/w 0 reserved 6 clkgen_rst r/w 0 clock controller 7 pinctrl_rst r/w 0 pin controller 8 rtc_rst r/w 0 rtc 9 uart0_rst r/w 0 uart0 10 uart1_rst r/w 0 uart1 11 spi0_rst r/w 0 spi0 12 spi1_rst r/w 0 spi1 13 i2c0_rst r/w 0 i2c0 14 i2c1_rst r/w 0 i2c1 15 i2sout_rst r/w 0 i2s output 16 cdd_rst r/w 0 cd-dsp 17 adc_rst r/w 0 adc 18 remap_rst r/w 0 remap 19 rcr_rst r/w 0 rcr 20 gpio0_rst r/w 0 gpio0 21 gpio1_rst r/w 0 gpio1 22 dmac_rst r/w 0 dmac 23 cdr_rst r/w 0 cd-rom 24 sdrc_rst r/w 0 sdram controller 25 - r/w 0 reserved 26 sdio_rst r/w 0 sdio i/f 27 - r/w 0 reserved 28 sfl_rst r/w 0 serial flash i/f 29 - r/w 0 reserved 30 - r/w 0 reserved bits name direction reset description 0 usbd_rst r/w 0 usb connect detector 0: reset cleared (normal operation) 1: reset set 1 usbc_rst r/w 0 usb controller 0: reset cleared (normal operation) 1: reset set 2 usbphy_rst r/w 0 usb phy 0: reset cleared (normal operation) 1: reset set 3 usb_suspend r/w 0 usb suspend 0 : suspend cleared (normal operation) 1 : suspend set downloaded from: http:///
366/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 operational notes 1. power on reset please keep the terminal resetx at the low level when the power supply starts. after completely starting up 3.3v system power supply, afterwards, please make the termin al resetx high level after 300us after the 32.768khz and 16.9344mhz oscillation is steady. moreover, please make the terminal resetx low level during 300us or more when resetting it while operating. 2. about compatibility in usb memory device and sd memory card according to the file structure and communication speed of usb memory, sd memory card, this lsi might not play back correctly. 3. about compatibility in bluetooth device according to the bluetooth device, this lsi might not play back correctly. 4. about turning on the power supply current rush might flow momentarily by the order of turning on the power supply and the delay in ic with two or more power supplies, and note the capacity of the power supply coupling, the power supply, and width and drawing the gnd pattern wiring. 5. about absolute maximum rating when the absolute maximum rating such as the applied voltage and the ranges of the operating temperature is exceeded, lsi might be destroyed. please do not apply eithervoltage or temperature that exceeds the absolute maximum rating. please execute physical measures for safety such as fuse when it is thought to exceed the absolute maximum rating, and examine it so that the condition to exceed the absolute maximum rating is not applied to lsi. 6. power supply power and ground line must be designed as low impedance in the pcb. print patterns if digital power supply and analog power supply must be separated even if these have same voltage level. print patterns for ground must be designed as same as power supply. these considerations avoid analog circui ts from the digital circuit noise. all pair of power supply and ground must have their own de-coupling capacitor. those capacitor should be checked about their specification, etc. (nominal electrolytic capacitor degrades its capacity at low temperature) and choose the constant of an electrolytic capacitor. 7. about gnd voltage in any state of operation, it must be the lowest voltage about the voltage of the terminal gnd. please actually confirm the voltage of each terminal is not a voltage that is lower than the terminal gnd including excessive phenomenon. 8. about design of overheating malfunction preventive circuit please design overheating malfunction preventive circuit with an enough margin in consideration of a permissible loss in actual usage. 9. about the short between terminals and the mounting by mistake please note that the direction and the gap of position of lsi must be enough when you mount on the substrate. lsi might be destroyed when mounting by mistake and energizing. mor eover, lsi might be destroyed when short-circuited by entering of the foreign substances between the terminal and gnd, between terminals, between the terminal and the power supply of lsi. 10. about operation in strong electromagnetic field lsi might malfunction when operating in strong magnetic fiels. please evaluate before usage. 11. about 2x speed recording recording to a memory with slow access speed may require data connection operation. 2x speed recording to all the memories cannot be guaranteed. 12. power off or memory disconnection under memory writing the sudden power off or memory disconnection during recording or file write operation to a memory may break the data in a memory. 13. browsing operation with a memory with slow access speed, browsing operation during music playing may generate skipping. downloaded from: http:///
367/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 operational notes C continued 14. cd-rom playing cd-rom playing operation is premised on data being inputted so that an internal data buffer may not become empty. when an input does not meet the deadline and internal data buffers become empty, skipping occurs. 15. playing time of mp3 file the playing time when mp3 file playing may shift when fast forward playing, rewind playi ng, and vbr playing. 16. write-in operation exceeding memory size writing to a file when memory size is exceeded is not supported. 17. write-in operation of the file size exceeding fat specification writing to a file when file size is exceeded is not supported. 18. about i 2 c format i/f although this lsi has adopted the i 2 c format, the level shifter circuit is not built in. for this reason, level shifter is needed for connection with the device besides the range of operating power supply voltage of this lsi. status of this document the japanese version of this document is fo rmal specification. a cu stomer may use this translation version only for a reference to help reading the formal version. if there are any differences in translation version of this document formal version takes priority downloaded from: http:///
368/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 ordering information b m 9 4 8 0 1 k u t - z part number package tqfp128um , supply with tray marking diagram tqfp128um (top view) bm94801 part number marking lot number 1pin mark downloaded from: http:///
369/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 physical dimension, tape and reel information package name tqfp128um ? order quantity needs to be multiple of the minimum quantity. tray (with dry pack) containerquantity direction of feed 500pcs direction of product is fixed in a tray 1pin downloaded from: http:///
370/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 revision history date revision changes 6.sep.2013 001 new release 1.oct.2013 002 p. 186 : removed about the correspondence beyond 88.2khz p. 186 : removed 16.2.8 interpolating filter (adc) p. 275 : cd-dsp command:&h85[2:0] is modified to h4w2, h4w1, h4w0 p. 284 : cd-dsp command:&h9c[3:0] modified rfoffset equation to vc+((15-&h9c[3:0]).0.20-2.0).vdd/3 p. 304 : cd-dsp command:&hd4[3:0] "3: nothing" is added p. 333 : wdt_ccvr register initial value is modified to 0x7fff_ffff p. 338 : component version register register initial value is modified to 0x3230332a p. 353 : clk_set3 register bit [3:0] is modified to the un-use the addition of other details explanations and indication composition become proper. 18.apr.2014 003 p.008 : the addition of the function explanations about no.100 usb rexti. p.009 - p010 : the addition of the electrical characteristics measurement condition about rexti pins external resistance. downloaded from: http:///
371/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 table of contents general de scription............................................................................................................ ......................................................... 1 features 1 package 1 application ............................................................................................................................... .................................................... 1 applicatio n block ............................................................................................................. ............................................................ 1 arm946es microproc essor core .................................................................................................. .......................................... 2 sdram ............................................................................................................................... ..................................................... 2 initial prog ram ro m ........................................................................................................... ..................................................... 2 remap ......................................................................................................................... ........................................................... 2 shadow sram ................................................................................................................... .................................................. 2 program sram .................................................................................................................. ..................................................... 2 data sram ..................................................................................................................... ......................................................... 2 sdram controller .............................................................................................................. ..................................................... 2 amba .......................................................................................................................... ............................................................ 2 interrupt controller .......................................................................................................... ......................................................... 2 dma controller ................................................................................................................ ........................................................ 2 gpio ............................................................................................................................... ......................................................... 2 pin controller ................................................................................................................ ........................................................... 3 usb 2.0 dual role (hos t/device) controller .................................................................................... ....................................... 3 sd i/f ........................................................................................................................ .............................................................. 3 quad spi i/f .................................................................................................................. .......................................................... 3 ssi master .................................................................................................................... ........................................................... 3 ssi slave ..................................................................................................................... ............................................................ 3 i2c i/f (master/slave) ............................................................................................................................... ............................... 3 uart i/f ...................................................................................................................... ............................................................ 4 i2s input i/f ................................................................................................................. ............................................................ 4 i2s output i/f ................................................................................................................ .......................................................... 4 cd servo controller ............................................................................................................................... .................................. 4 cd-rom decoder ................................................................................................................ ................................................... 4 general purpose a/d conv erter ................................................................................................. ............................................. 4 timer ......................................................................................................................... .............................................................. 4 watchdog timer ................................................................................................................ ....................................................... 4 real time clock ............................................................................................................... ....................................................... 4 remote controller receiver (rcr) .............................................................................................. ........................................... 5 clock generator ............................................................................................................... ....................................................... 5 reset gener ator ............................................................................................................... ....................................................... 5 pll ........................................................................................................................... ............................................................... 5 power supply voltage ............................................................................................................................... ............................... 5 pin assi gnment ................................................................................................................ ........................................................... 6 pin description ............................................................................................................... ............................................................. 7 electrical characteristics ............................................................................................................................... .................................. 9 absolute maximum ratings (ta ? 25 ? c) ............................................................................................................................ ............... 9 recommended operating conditions (ta=25c) .................................................................................... ........................................ 9 electrical characteristics ............................................................................................................................... .................................. 9 electrical characteri stics C continued ........................................................................................ ................................................... 10 electrical characteri stics C continued ........................................................................................ ................................................... 11 application in formation ....................................................................................................... .......................................................... 12 clock and reset ............................................................................................................... ......................................................... 12 1. amba .......................................................................................................................... ....................................................... 13 1.1. features ...................................................................................................................................................................... 13 1.2. description ................................................................................................................... ............................................... 14 1.2.1. block diagram ................................................................................................................. .................................... 14 1.2.2. memory map .................................................................................................................... .................................... 15 1.2.3. arm ahb ............................................................................................................................... .............................. 15 1.2.4. dmac ahb ...................................................................................................................... .................................... 15 1.2.5. pdmac ahb ............................................................................................................................... ......................... 16 1.2.6. apb ........................................................................................................................... .......................................... 16 1.2.7. mux ........................................................................................................................... .......................................... 16 1.3. i/o si gnals ................................................................................................................... ............................................... 17 2. remap ......................................................................................................................... ..................................................... 19 2.1. features ...................................................................................................................................................................... 19 2.2. description ................................................................................................................... ............................................... 19 2.2.1. outline blo ck diagram ......................................................................................................... ................................ 19 2.2.2. description ................................................................................................................... ........................................ 19 2.3. i/o si gnals ................................................................................................................... ............................................... 19 2.4. register ...................................................................................................................... ................................................ 20 2.4.1. memory map .................................................................................................................... .................................... 20 2.4.2. register detail ............................................................................................................... ...................................... 20 3. sdram controller ............................................................................................................................... ............................... 21 downloaded from: http:///
372/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 3.1. feature ....................................................................................................................... ................................................ 21 3.2. description ................................................................................................................... ............................................... 21 3.2.1. fifo .......................................................................................................................... .......................................... 21 3.2.2. read_pipe/wr ite_pi pe .......................................................................................................... ........................ 21 3.2.3. sdram ......................................................................................................................... ....................................... 22 3.2.4. external memory interface ..................................................................................................... .............................. 28 3.3. i/o si gnal .................................................................................................................... ................................................ 29 3.4. register ...................................................................................................................... ................................................ 32 3.4.1. memory map .................................................................................................................... .................................... 32 3.4.2. register detail ............................................................................................................... ...................................... 32 4. interrupt controller .......................................................................................................... ................................................... 37 4.1. features ...................................................................................................................................................................... 37 4.2. description ................................................................................................................... ............................................... 37 4.2.1. irq ........................................................................................................................... ........................................... 37 4.2.2. fiq ....................................................................................................................................................................... 37 4.2.3. irq interrupt output .......................................................................................................... .................................. 37 4.2.4. irq interrupt polari ty ........................................................................................................ ................................... 37 4.2.5. irq software interrupt ........................................................................................................ ................................. 37 4.2.6. enable irq an d irq mask ....................................................................................................... ........................... 37 4.2.7. irq interrupt priority level .................................................................................................. ................................ 38 4.2.8. irq interrupt status .......................................................................................................... ................................... 38 4.2.9. irq interrupt vector .......................................................................................................... ................................... 38 4.2.10. fiq interrupt output .......................................................................................................... ................................... 39 4.2.11. fiq interrupt polari ty ........................................................................................................ ................................... 39 4.2.12. fiq software interrupt ........................................................................................................ ................................. 40 4.2.13. enable fiq and fiq ma sk ....................................................................................................... ............................ 40 4.2.14. fiq interrupt status .......................................................................................................... ................................... 40 4.3. i/o si gnal .................................................................................................................... ................................................ 40 4.4. register map ............................................................................................................................... ................................ 41 4.4.1. memory map .................................................................................................................... .................................... 41 4.4.2. register detail ............................................................................................................... ...................................... 43 5. dmac (direct memory access controller) ........................................................................................ ................................. 46 5.1. feature ....................................................................................................................... ................................................ 46 5.1.1. summary ....................................................................................................................... ...................................... 46 5.1.2. address generation ............................................................................................................ ................................. 46 5.1.3. channel buffer ring ............................................................................................................................... .............. 46 5.1.4. channel control ............................................................................................................... .................................... 46 5.1.5. flow control ............................................................................................................................... .......................... 46 5.1.6. handshaking ................................................................................................................... ..................................... 46 5.1.7. interrupt ..................................................................................................................... .......................................... 46 5.2. description ................................................................................................................... ............................................... 47 5.2.1. transfer hierarchy ............................................................................................................ ................................... 47 5.2.2. handshaking interface ......................................................................................................... ................................ 52 5.2.3. transfer using handshaking .................................................................................................... ........................... 52 5.3. i/o si gnal .................................................................................................................... ................................................ 53 5.4. register ...................................................................................................................... ................................................ 55 5.4.1. memory map .................................................................................................................... .................................... 55 5.4.2. register detail ............................................................................................................... ...................................... 58 6. gpio0/gpio1 ................................................................................................................... ................................................. 67 6.1. feature ....................................................................................................................... ................................................ 67 6.2. description ................................................................................................................... ............................................... 68 6.2.1. data flow and data control .................................................................................................... ............................. 68 6.2.2. interrupt output ............................................................................................................................... ..................... 69 6.2.3. debounce fu nction ............................................................................................................. ................................. 69 6.3. i/o si gnal .................................................................................................................... ................................................ 71 6.4. register ...................................................................................................................... ................................................ 72 6.4.1. memory map .................................................................................................................... .................................... 72 6.4.2. register detail ............................................................................................................... ...................................... 73 7. pin controller ................................................................................................................ ..................................................... 75 7.1. features ...................................................................................................................................................................... 75 7.2. description ................................................................................................................... ............................................... 75 7.2.1. outline circui t diagram ....................................................................................................... ................................. 75 7.3. i/o si gnals ................................................................................................................... ............................................... 75 7.4. register ...................................................................................................................... ................................................ 75 7.4.1. memory map .................................................................................................................... .................................... 75 7.4.2. register detail ............................................................................................................... ...................................... 76 8. usb 2.0 dual role (hos t/device) controller .................................................................................... .................................. 78 8.1. outline ....................................................................................................................... ................................................. 78 8.1.1. block chart ................................................................................................................... ....................................... 78 8.1.2. utm syncroni zation ............................................................................................................ ........................ 78 downloaded from: http:///
373/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 8.1.3. packet encodi ng/decoding ...................................................................................................... ................ 78 8.1.4. endpoint controllers .......................................................................................................... .................... 78 8.1.5. cpu interface ................................................................................................................. ............................... 78 8.1.6. ram controller ................................................................................................................ ........................... 78 8.1.7. musbhdrc configuration ........................................................................................................ .......................... 79 8.1.8. usb connect detector........................................................................................................... .............................. 79 8.1.9. usb-reset ..................................................................................................................... ...................................... 81 8.2. i/o si gnals ................................................................................................................... ............................................... 81 8.3. register (f8000000 mentor usb controller) ..................................................................................... ......................... 83 8.3.1. memory map .................................................................................................................... .................................... 83 8.3.2. resister detail ............................................................................................................... ...................................... 86 8.4. register (f8100000 usb connect detector) ...................................................................................... ...................... 103 8.4.1. memory map .................................................................................................................... .................................. 103 8.4.2. register detail ............................................................................................................... .................................... 103 9. sd i/f ........................................................................................................................ ....................................................... 105 10. quad spi i/f .................................................................................................................. .................................................. 106 10.1. features ...................................................................................................................... .............................................. 106 10.2. description ................................................................................................................... ............................................. 106 10.2.1. block diagram ................................................................................................................. .................................. 106 10.2.2. connection ............................................................................................................................... .......................... 106 10.2.3. command & addr ess decoder ..................................................................................................... ..................... 107 10.2.4. control register .............................................................................................................. ................................... 107 10.2.5. data fifo ..................................................................................................................... ..................................... 107 10.2.6. spi format ............................................................................................................................... .......................... 107 10.2.7. transfer modes ................................................................................................................ .................................. 107 10.2.8. interrupt ..................................................................................................................... ........................................ 108 10.3. i/o si gnals ................................................................................................................... ............................................. 108 10.4. register ...................................................................................................................... .............................................. 109 10.4.1. memory map .................................................................................................................... .................................. 109 10.4.2. register detail ............................................................................................................... .................................... 109 11. ssi master .................................................................................................................... ................................................... 113 11.1. feature ....................................................................................................................... .............................................. 113 11.2. description ................................................................................................................... ............................................. 113 11.2.1. serial protocol ............................................................................................................... .................................... 113 11.2.2. clock ratio ................................................................................................................... ..................................... 113 11.3. i/o si gnal .................................................................................................................... .............................................. 114 11.4. register ...................................................................................................................... .............................................. 116 11.4.1. memory map .................................................................................................................... .................................. 116 11.4.2. register detail. .............................................................................................................. .................................... 118 12. ssi slave ..................................................................................................................... .................................................... 124 12.1. feature ....................................................................................................................... .............................................. 124 12.2. description ................................................................................................................... ............................................. 124 12.2.1. clock ration .................................................................................................................. .................................... 124 12.3. i/o si gnal .................................................................................................................... .............................................. 125 12.4. register ...................................................................................................................... .............................................. 127 12.4.1. memory map .................................................................................................................... .................................. 127 12.4.2. register detail ............................................................................................................... .................................... 128 13. i2c0/i2c1 ..................................................................................................................... .................................................... 133 13.1. feature ....................................................................................................................... .............................................. 133 13.2. description ................................................................................................................... ............................................. 133 13.2.1. i2c protocol .................................................................................................................. ..................................... 133 13.2.2. arbitration and clock generation .............................................................................................. ......................... 136 13.2.3. operation mode ................................................................................................................ ................................. 137 13.2.4. spike control ................................................................................................................. .................................... 139 13.3. i/o si gnal .................................................................................................................... .............................................. 140 13.4. register ...................................................................................................................... .............................................. 142 13.4.1. memory map .................................................................................................................... .................................. 142 13.4.2. register detail. .............................................................................................................. .................................... 144 14. uart0/uart1 ................................................................................................................... .............................................. 153 14.1. feature ....................................................................................................................... .............................................. 153 14.2. description ................................................................................................................... ............................................. 153 14.2.1. uart serial protocol .......................................................................................................... ............................... 153 14.2.2. buffer for transmi ssion and rece ption ......................................................................................... ..................... 154 14.2.3. interrupt ..................................................................................................................... ........................................ 154 14.2.4. auto-flow control (uart0 only) ................................................................................................ ....................... 155 14.3. i/o si gnal .................................................................................................................... .............................................. 156 14.4. register ...................................................................................................................... .............................................. 158 14.4.1. memory map .................................................................................................................... .................................. 158 14.4.2. register detail ............................................................................................................... .................................... 159 15. i2s input i/f and cd-rom de coder .............................................................................................. .................................. 167 downloaded from: http:///
374/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 15.1. features ...................................................................................................................... .............................................. 167 15.2. description ................................................................................................................... ............................................. 167 15.2.1. block diagram ................................................................................................................. .................................. 167 15.2.2. serial-to-parallel conversion through 3-wire (3-line) input inte rface ......................................................... ...... 168 15.2.3. inreqi ........................................................................................................................ ...................................... 168 15.2.4. bfullo ........................................................................................................................ ..................................... 168 15.2.5. receive buffer ................................................................................................................ ................................... 168 15.2.6. cd-rom i nput .................................................................................................................. ................................. 169 15.2.7. error corre ction .............................................................................................................. ................................... 171 15.2.8. sub-q data and cd-text data acquisition ....................................................................................... ................. 172 15.3. i/o si gnals ................................................................................................................... ............................................. 173 15.4. register ...................................................................................................................... .............................................. 174 15.4.1. memory map .................................................................................................................... .................................. 174 15.4.2. register detail ............................................................................................................... .................................... 175 16. i2s output i/f .................................................................................................................................................................. 185 16.1. features .............................................................................................................................. ..................................... 185 16.2. description ................................................................................................................... ............................................. 185 16.2.1. block diagram ................................................................................................................. .................................. 185 16.2.2. dma i/f ....................................................................................................................... ....................................... 186 16.2.3. clock selector ................................................................................................................ .................................... 188 16.2.4. i/o bus interface ............................................................................................................. ................................... 188 16.2.5. audio data read (i2s) ......................................................................................................... .............................. 188 16.2.6. interpolating filter .......................................................................................................... .................................... 188 16.2.7. audio data read (adc) ............................................................................................................................... ...... 189 16.2.8. dac i/f ....................................................................................................................... ....................................... 189 16.2.9. output waveforms .............................................................................................................. ............................... 189 16.3. i/o si gnals ................................................................................................................... ............................................. 190 16.4. register ...................................................................................................................... .............................................. 191 16.4.1. memory map .................................................................................................................... .................................. 191 16.4.2. register detail ............................................................................................................... .................................... 192 17. cd servo c ontroller ........................................................................................................... .............................................. 199 17.1. features ...................................................................................................................... .............................................. 199 17.2. description ................................................................................................................... ............................................. 199 17.2.1. block diagram ................................................................................................................. .................................. 199 17.2.2. window ........................................................................................................................ ...................................... 200 17.2.3. error detection and correction (ecc) block ...................................................................................................... 201 17.3. rf signal gen (analog) + digital servo signal processor ........................................................................................ 202 17.3.1. clv and pll .............................................................................................................................. ....................... 203 17.3.2. functional description of each block .......................................................................................... ........................ 204 17.3.3. operation mode ................................................................................................................ ................................. 207 17.3.4. a/d converter for servo system ................................................................................................ ........................ 209 17.3.5. ats comparator ................................................................................................................ ................................ 211 17.3.6. tzc comparator ................................................................................................................ ................................ 212 17.3.7. generation of cout si gnal ..................................................................................................... .......................... 213 17.3.8. basic block of serv o filter circuit ........................................................................................... ........................... 214 17.3.9. focus servo filter ............................................................................................................ .................................. 215 17.3.10. tracking serv o filter ......................................................................................................... ............................. 217 17.3.11. sled servo filter ............................................................................................................. ................................ 220 17.3.12. servo cont roller .............................................................................................................. ................................ 220 17.3.13. focus search .................................................................................................................. ................................ 221 17.3.14. fzc comparator ................................................................................................................ ............................ 223 17.3.15. cd-rw detection and gain setting .............................................................................................. .................. 224 17.3.16. track jump ............................................................................................................................... ...................... 225 17.3.17. tracking half-wa ve brake m ode ................................................................................................. ............ 230 17.3.18. tracking gain-up mode ......................................................................................................... ........................ 230 17.3.19. sled intermittent feed ........................................................................................................ ............................ 231 17.3.20. auto adjustment and measur ement ............................................................................................... ................ 232 17.3.21. detection of defect disc and countermeasures .............................................................................................. 245 17.3.22. pre-serv o amp ................................................................................................................. ............................. 246 17.3.23. yflag gener ator ............................................................................................................... ............................ 255 17.3.24. a precaution in pcb la yout. (recomme ndation) .................................................................................. ............ 256 17.4. i/o si gnals ................................................................................................................... ............................................. 257 17.5. register ...................................................................................................................... .............................................. 258 17.5.1. memory map .................................................................................................................... .................................. 258 17.5.2. register detail ............................................................................................................... .................................... 259 17.5.3. cd-dsp status ................................................................................................................. ................................. 262 17.5.4. inside signal monitor output .................................................................................................. ............................. 263 17.5.5. cd-dsp command ............................................................................................................................... ............. 266 18. general-purpose a/ d conver ter ................................................................................................. ..................................... 323 18.1. features ...................................................................................................................... .............................................. 323 downloaded from: http:///
375/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 18.2. description ................................................................................................................... ............................................. 323 18.2.1. block diagram ................................................................................................................. .................................. 323 18.2.2. basic operation ............................................................................................................... .................................. 324 18.2.3. input channe l setti ng ......................................................................................................... ............................... 324 18.2.4. data output coding setting .................................................................................................... ........................... 324 18.2.5. data output to i2s output block ............................................................................................... ......................... 325 18.3. i/o si gnals ................................................................................................................... ............................................. 326 18.4. register ...................................................................................................................... .............................................. 326 18.4.1. memory map .................................................................................................................... .................................. 326 18.4.2. register detail ............................................................................................................... .................................... 327 19. timer ......................................................................................................................... ....................................................... 329 19.1. feature ....................................................................................................................... .............................................. 329 19.2. description ................................................................................................................... ............................................. 329 19.2.1. basic operation ............................................................................................................... .................................. 329 19.2.2. operation mode ................................................................................................................ ................................. 329 19.2.3. interrupt signal .............................................................................................................. .................................... 329 19.3. i/o si gnals ................................................................................................................... ............................................. 330 19.4. register ...................................................................................................................... .............................................. 332 19.4.1. memory map .................................................................................................................... .................................. 332 19.4.2. register detail ............................................................................................................... .................................... 333 20. watchdog timer ................................................................................................................ ............................................... 335 20.1. feature ....................................................................................................................... .............................................. 335 20.2. description ................................................................................................................... ............................................. 335 20.2.1. counter ....................................................................................................................... ....................................... 335 20.2.2. clock enable ............................................................................................................................... ....................... 335 20.2.3. reset pulse length ............................................................................................................ ............................... 335 20.3. i/o si gnals ................................................................................................................... ............................................. 336 20.4. register map ............................................................................................................................... .............................. 337 20.4.1. memory map .................................................................................................................... .................................. 337 20.4.2. register detail ............................................................................................................... .................................... 337 21. real time clock ............................................................................................................... ................................................ 339 21.1. feature ....................................................................................................................... .............................................. 339 21.2. description ................................................................................................................... ............................................. 339 21.2.1. clock ......................................................................................................................... ......................................... 339 21.3. i/o si gnal .................................................................................................................... .............................................. 340 21.4. register ...................................................................................................................... .............................................. 340 21.4.1. memory map .................................................................................................................... .................................. 340 21.4.2. register details .............................................................................................................. ................................... 341 22. remote controller receiver (rcr) .............................................................................................. .................................... 343 22.1. features ...................................................................................................................... .............................................. 343 22.2. description ................................................................................................................... ............................................. 343 22.2.1. block diagram ................................................................................................................. .................................. 343 22.2.2. aeha communicati on format ..................................................................................................... ...................... 343 22.2.3. basic operation ............................................................................................................... .................................. 344 22.2.4. operational clock ............................................................................................................. ................................. 344 22.2.5. inversion of input signal po larity ............................................................................................ ........................... 344 22.2.6. noise filter ............................................................................................................................... .......................... 344 22.2.7. pulse width measur ement c ounter ............................................................................................... .................... 344 22.2.8. interrupts ............................................................................................................................... ............................. 344 22.2.9. received data ................................................................................................................. .................................. 345 22.2.10. handling of e rror sign al ...................................................................................................... ........................... 345 22.3. i/o si gnals ................................................................................................................... ............................................. 345 22.4. register ...................................................................................................................... .............................................. 346 22.4.1. memory map .................................................................................................................... .................................. 346 22.4.2. register detail ............................................................................................................... .................................... 346 23. clock generator ............................................................................................................... ................................................ 349 23.1. features ...................................................................................................................... .............................................. 349 23.2. description ................................................................................................................... ............................................. 349 23.2.1. block diagram ................................................................................................................. .................................. 349 23.2.2. input contro l bloc k ........................................................................................................... ................................. 349 23.2.3. clkdiv2_div32 and cl kdiv2_4 bl ocks ............................................................................................ ..................... 349 23.2.4. syssel block .................................................................................................................. .................................... 349 23.2.5. clksel block .................................................................................................................. ..................................... 350 23.2.6. clock control sign al generator ................................................................................................ ......................... 350 23.2.7. power-down mode ............................................................................................................... ............................. 350 23.2.8. clocks in log ic bl ock ......................................................................................................... ................................ 350 23.2.9. sdram clocks .................................................................................................................. ................................ 351 23.2.10. audio clocks .................................................................................................................. ................................ 351 23.3. i/o si gnals ................................................................................................................... ............................................. 352 23.4. register ...................................................................................................................... .............................................. 353 downloaded from: http:///
376/376 datasheet datasheet BM94801KUT tsz02201-0v2v0e600300-1-2 18.apr.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 15 001 23.4.1. memory map .................................................................................................................... .................................. 353 23.4.2. register detail ............................................................................................................... .................................... 354 24. reset generator ............................................................................................................................... ................................ 362 24.1. features ...................................................................................................................... .............................................. 362 24.2. description ................................................................................................................... ............................................. 362 24.2.1. outline circui t diagram ....................................................................................................... ............................... 362 24.2.2. description ................................................................................................................... ...................................... 362 24.2.3. timing chart .................................................................................................................. .................................... 362 24.2.4. denoising circuit ............................................................................................................. ................................... 363 24.2.5. system rese t counter .......................................................................................................... ............................. 363 24.2.6. phy reset counter ............................................................................................................. .............................. 363 24.2.7. wdt reset ..................................................................................................................... ................................... 363 24.3. i/o si gnals ................................................................................................................... ............................................. 364 24.4. register ...................................................................................................................... .............................................. 364 24.4.1. memory map .................................................................................................................... .................................. 364 24.4.2. register detail ............................................................................................................... .................................... 365 operational notes ............................................................................................................. .......................................................... 366 ordering information .............................................................................................................................. .................................. 368 marking diagram .............................................................................................................................. ......................................... 368 physical dimension, tape and reel information ................................................................................................................... 369 revision history .............................................................................................................................. ......................................... 370 table of contents ............................................................................................................. ........................................................... 371 downloaded from: http:///
datasheet datasheet notice C ge rev.002 ? 2013 rohm co., ltd. all rights reserved. notice precaution on using rohm products 1. our products are designed and manufac tured for application in ordinary elec tronic equipments (such as av equipment, oa equipment, telecommunication equipment, home electroni c appliances, amusement equipment, etc.). if you intend to use our products in devices requiring ex tremely high reliability (such as medical equipment (note 1) , transport equipment, traffic equipment, aircraft/spacecra ft, nuclear power controllers, fuel c ontrollers, car equipment including car accessories, safety devices, etc.) and whose malfunction or failure may cause loss of human life, bodily injury or serious damage to property (specific applications), please consult with the rohm sale s representative in advance. unless otherwise agreed in writing by rohm in advance, rohm shall not be in any way responsible or liable for any damages, expenses or losses incurred by you or third parties arising from the use of any ro hms products for specific applications. (note1) medical equipment classification of the specific applications japan usa eu china class class class b class class | class 2. rohm designs and manufactures its products subject to strict quality control system. however, semiconductor products can fail or malfunction at a certain rate. please be sure to implement, at your own responsibilities, adequate safety measures including but not limited to fail-safe desi gn against the physical injury, damage to any property, which a failure or malfunction of our products may cause. the following are examples of safety measures: [a] installation of protection circuits or other protective devices to improve system safety [b] installation of redundant circuits to reduce the impact of single or multiple circuit failure 3. our products are designed and manufactured for use under standard conditions and not under any special or extraordinary environments or conditio ns, as exemplified below. accordin gly, rohm shall not be in any way responsible or liable for any damages, expenses or losses arising from the use of an y rohms products under any special or extraordinary environments or conditions. if you intend to use our products under any special or extraordinary environments or conditions (as exemplified below), your independent verification and confirmation of product performance, reliability, etc, prior to use, must be necessary: [a] use of our products in any types of liquid, incl uding water, oils, chemicals, and organic solvents [b] use of our products outdoors or in places where the products are exposed to direct sunlight or dust [c] use of our products in places where the products ar e exposed to sea wind or corrosive gases, including cl 2 , h 2 s, nh 3 , so 2 , and no 2 [d] use of our products in places where the products are exposed to static electricity or electromagnetic waves [e] use of our products in proximity to heat-producing components, plastic cords, or other flammable items [f] sealing or coating our products with resin or other coating materials [g] use of our products without cleaning residue of flux (ev en if you use no-clean type fluxes, cleaning residue of flux is recommended); or washing our products by using water or water-soluble cleaning agents for cleaning residue after soldering [h] use of the products in places subject to dew condensation 4. the products are not subjec t to radiation-proof design. 5. please verify and confirm characteristics of the final or mounted products in using the products. 6. in particular, if a transient load (a large amount of load applied in a short per iod of time, such as pulse. is applied, confirmation of performance characteristics after on-boar d mounting is strongly recomm ended. avoid applying power exceeding normal rated power; exceeding the power rating under steady-state loading c ondition may negatively affect product performance and reliability. 7. de-rate power dissipation (pd) depending on ambient temper ature (ta). when used in seal ed area, confirm the actual ambient temperature. 8. confirm that operation temperat ure is within the specified range described in the product specification. 9. rohm shall not be in any way responsible or liable for fa ilure induced under deviant condi tion from what is defined in this document. precaution for mounting / circuit board design 1. when a highly active halogenous (chlori ne, bromine, etc.) flux is used, the resi due of flux may negatively affect product performance and reliability. 2. in principle, the reflow soldering method must be used; if flow soldering met hod is preferred, please consult with the rohm representative in advance. for details, please refer to rohm mounting specification downloaded from: http:///
datasheet datasheet notice C ge rev.002 ? 2013 rohm co., ltd. all rights reserved. precautions regarding application examples and external circuits 1. if change is made to the constant of an external circuit, pl ease allow a sufficient margin considering variations of the characteristics of the products and external components, including transient characteri stics, as well as static characteristics. 2. you agree that application notes, re ference designs, and associated data and in formation contained in this document are presented only as guidance for products use. theref ore, in case you use such information, you are solely responsible for it and you must exercise your own independent verification and judgment in the use of such information contained in this document. rohm shall not be in any way responsible or liable for any damages, expenses or losses incurred by you or third parties arising from the use of such information. precaution for electrostatic this product is electrostatic sensitive product, which may be damaged due to electrostatic discharge. please take proper caution in your manufacturing process and storage so that voltage exceeding t he products maximum rating will not be applied to products. please take special care under dry condit ion (e.g. grounding of human body / equipment / solder iron, isolation from charged objects, se tting of ionizer, friction prevention and temperature / humidity control). precaution for storage / transportation 1. product performance and soldered connections may deteriora te if the products are stor ed in the places where: [a] the products are exposed to sea winds or corros ive gases, including cl2, h2s, nh3, so2, and no2 [b] the temperature or humidity exceeds those recommended by rohm [c] the products are exposed to di rect sunshine or condensation [d] the products are exposed to high electrostatic 2. even under rohm recommended storage c ondition, solderability of products out of recommended storage time period may be degraded. it is strongly recommended to confirm sol derability before using products of which storage time is exceeding the recommended storage time period. 3. store / transport cartons in the co rrect direction, which is indicated on a carton with a symbol. otherwise bent leads may occur due to excessive stress applied when dropping of a carton. 4. use products within the specified time after opening a humidity barrier bag. baking is required before using products of which storage time is exceeding the recommended storage time period. precaution for product label qr code printed on rohm products label is for rohms internal use only. precaution for disposition when disposing products please dispose them proper ly using an authorized industry waste company. precaution for foreign exchange and foreign trade act since our products might fall under cont rolled goods prescribed by the applicable foreign exchange and foreign trade act, please consult with rohm representative in case of export. precaution regarding intellectual property rights 1. all information and data including but not limited to application example contained in this document is for reference only. rohm does not warrant that foregoi ng information or data will not infringe any intellectual property rights or any other rights of any third party regarding such information or data. rohm shall not be in any way responsible or liable for infringement of any intellectual property rights or ot her damages arising from use of such information or data.: 2. no license, expressly or implied, is granted hereby under any intellectual property rights or other rights of rohm or any third parties with respect to the information contained in this document. other precaution 1. this document may not be reprinted or reproduced, in whol e or in part, without prior written consent of rohm. 2. the products may not be disassembled, converted, modified, reproduced or otherwise changed without prior written consent of rohm. 3. in no event shall you use in any wa y whatsoever the products and the related technical information contained in the products or this document for any military purposes, incl uding but not limited to, the development of mass-destruction weapons. 4. the proper names of companies or products described in this document are trademarks or registered trademarks of rohm, its affiliated companies or third parties. downloaded from: http:///
datasheet datasheet notice C we rev.001 ? 2014 rohm co., ltd. all rights reserved. general precaution 1. before you use our pro ducts, you are requested to care fully read this document and fully understand its contents. rohm shall n ot be in an y way responsible or liabl e for fa ilure, malfunction or acci dent arising from the use of a ny rohms products against warning, caution or note contained in this document. 2. all information contained in this docume nt is current as of the issuing date and subj ec t to change without any prior notice. before purchasing or using rohms products, please confirm the la test information with a rohm sale s representative. 3. the information contained in this doc ument is provi ded on an as is basis and rohm does not warrant that all information contained in this document is accurate an d/or error-free. rohm shall not be in an y way responsible or liable for an y damages, expenses or losses incurred b y you or third parties resulting from inaccur acy or errors of or concerning such information. downloaded from: http:///

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